You need to design a heterogeneous reconfigurable architecture that can fit the Data Flow Graphs (DFGs)
given below. Select the functionality of computational units and size of the interconnect of your
reconfigurable architecture according to the DFGs that need to be mapped on to the architecture. The
datawidth of inputs is 4-bit. Use parameterized vhdl to design your computational units. Datawidth is used
as parameter. In order to build your reconfigurable architecture, following types of Computational Units
(CUs) can be used – (i) CUs that can perform all the operations including multiplication, (ii) CUs that can
perform all the operations excluding multiplication, (iii) CUs that can perform multiplications. Pass and
NOOP operations are supported in all three types of CUs.
For the technical report, explain the design decisions that are taken along the construction of the
reconfigurable architecture as explained in the class. Submit screenshots of simulation waveforms, vhdl
code, RTL schematic, and test bench of the design. Test your design using at least four test cases as
explained in the class (two for each DFG). Mark the test cases and show the corresponding inputs, You need to design a heterogeneous reconfigurable architecture that can fit the Data Flow Graphs (DFGs)
given below. Select the functionality of computational units and size of the interconnect of your
reconfigurable architecture according to the DFGs that need to be mapped on to the architecture. The
datawidth of inputs is 4-bit. Use parameterized vhdl to design your computational units. Datawidth is used
as parameter. In order to build your reconfigurable architecture, following types of Computational Units
(CUs) can be used – (i) CUs that can perform all the operations including multiplication, (ii) CUs that can
perform all the operations excluding multiplication, (iii) CUs that can perform multiplications. Pass and
NOOP operations are supported in all three types of CUs.
For the technical report, explain the design decisions that are taken along the construction of the
reconfigurable architecture as explained in the class. Submit screenshots of simulation waveforms, vhdl
code, RTL schematic, and test bench of the design. Test your design using at least four test cases as
explained in the class (two for each DFG). Mark the test cases and show the corresponding inputs,
expected outputs and simulated outputs for those cases. The source files should contain appropriate
comments for better understanding. Document the contributions of each team member. For the technical report, explain the design decisions that are taken along the construction of the
reconfigurable architecture as explained in the class. Submit screenshots of simulation waveforms, vhdl
code, RTL schematic, and test bench of the design. Test your design using at least four test cases as
explained in the class (two for each DFG). Mark the test cases and show the corresponding inputs,
expected outputs and simulated outputs for those cases. The source files should contain appropriate
comments for better understanding. Document the contributions of each team member.
expected outputs and simulated outputs for those cases. The source files should contain appropriate
comments for better understanding. Document the contributions of each team member.