What is a Verilog State Machine test bench? List its five key parts and explain each one of them.

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David · Accepted Answer

The test bench is used to supply the input parameters to any Verilog design. The state machine test bench used for the state machine to generate input vector and drive the state machine to the Input /Output ports of the design. 
The five key features of State machine Test Bench is as follows
1.Instatntiation: The test bench applies the stimulus (input vector) to the Design. To do this the Design must be instantiated in the test bench.
example:
//--------------------------------------------------------- //
 instantiate the Device Under Test (DUT)
 // using named instantiation 
count16 U1 ( .count(cnt_out), 
.count_tri(count_tri), 
.clk(clk_50), .rst_l(rst_l),
 .load_l(load_l), 
.cnt_in(count_in),
 .enable_l(enable_l), 
.oe_l(oe_l) ); 
//----------------------------------------------------------
2.

What is a Verilog State Machine test bench? List its five key parts and explain each one of them.

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