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HPL–CSP–90–42
11 October 1990
disk shuffling, stainless-steel moustrap springs, an AI
tool for writing monthly progress reports.)
Hypotheses
What exactly are the expected effects of the proposed
solution? (E.g. disk I/O time will increase to 2 seconds
per request.) Why is this?
What are plausible alternatives? How likely are they?
What’s good and bad about them by comparison with
what’s proposed? What have others done already? What
did they learn? (This is the “literature search” segment.)
Experiments
What will be done to test out the hypotheses? (E.g.
measurements, simulations, constructing code, thinking
eautiful thoughts, hard vacationing). How will this
confirm (or deny) the hypotheses? Why will the
conclusions be believable?
Who will work on this? For how long? What additional
equipment or other resources will be needed (e.g. loan
of a boa-constrictor for 2 weeks)?
Results
What will be the outcome of the work (papers, a working
system, a graph of ...)? When? What are the intermediate
milestones? How will we know when they are
complete?
What are the measures for success? (E.g. “faster”,
“smaller”, “more available”.) How will we know to
declare the project a success?
This note outlines what should be in the document that
describes the hopes and aspirations of a new CSP activity.
CSP project startup documents
John Wilkes
Concu
ent Computing Department
Hewlett-Packard Laboratories
The most successful of the projects that the CSP group
has engaged in over the years have begun by recording
their aspirations and intentions. When done well, this
has resulted in a clear set of goals that have guided the
project and helped determine when co
ective o
supportive action is needed to help get things back on
track. Since this seems like a Good Thing, I propose that
we require a CSP startup document for all CSP-initiate
activities.
This note is intended as an aide memoire to people writing
a startup document. It indicates the expected contents of
such documents, in the form of a checklist of questions
that should be answered.
The basic idea is to think of the project as a hypothesis-
experiment-conclusion chain, with the conclusion being
a justified solution to some interesting problem.
What follows are outlines for the five major portions that
a project startup document should contain. You can
always add more if you like (much more, if you insist),
ut try hard to include some sort of answer to these
questions.
Problem statement
What is the problem that this project is going to address?
Does it matter: why is the problem important? Who will
enefit when the problem is solved (e.g. CSP/DataMesh,
HPL, IBM)?
Proposal
What is the basic approach, method, idea or tool that’s
eing suggested to solve the problem? (E.g. dynamic
Coen180 project proposal
1
Project Proposal
Project Topic: NAND Flash Memory
Project idea: Design a NAND Flash Memory
Questions:
- What is NAND Flash Memory?
+ NAND flash memory is a storage technology that does not need power to store
data. NAND flash helps reduce the cost per bit and increase maximum chip
capacity so that flash memory is popular. We can see it in our smartphones, smart
televisions, and computers.
- How does NAND Flash work?
+ NAND flash will rely on electric circuits to store and retrieve your data. The data
stored on NAND Flash is represented by electrical charges that are stored in each
NAND cell.
- Compare NAND Flash Memory with NOR Flash Memory
+ Flash memory architecture is based on floating gate technology.
+ In NOR flash memory, each memory cell is linked to the floating gate.
+ In NAND flash memory, several memory cells are connected in parallel.
2
+
- Why is NAND Flash Memory better than NOR Flash Memory?
+ NAND Flash memory cells are smaller and cheaper, yet they have highe
program/erase speed.
+ Density of NAND memory is much higher than the density of NOR flash
memory.
+ It is easier to program in NAND Memory.
Comment from the instructor: This is a good area, but I’d suggest trying to be
more specific about performance questions (e.g., if you conclude that NAND is
etter than NOR, in a particular way, then dig into multiple sources (o
conduct a simple simulation/test) to establish by how much. For the progress
eport, I’ll expect a bit more detail on your expected final report contents.
3
FLASH
FLASH 1
Floating Gate Basics
A typical flash memory cell uses a floating gate to store a bit by the presence or
absence of a charge. If the floating gate is not charged (i.e. neutral), then the device
operates almost like a normal MOSFET, a positive charge in the control gate
creates a channel in the p-substrate that ca
ies a cu
ent from source to drain. If
however the floating gate is negatively charged, then this charge shields the
channel region somewhat from the control gate and prevents the formation of a
channel between source and drain. The threshold voltage is the voltage applied to
the control gate at which a transistor becomes conductive. The presence or the
absence of a charge results in a more positive or more negative threshold voltage.
In flash memory lingo, programming (putting electrons into the floating gate)
means writing a 0, erasing (removing the charge from the floating gate) means
esetting the flash memory contents to 1; or in other words: a programmed cell
stores a logic 0, an erased (a.k.a. flashed) cell stores a logic 1.
These notes were originally created by Professor Thomas Schwarz, S.J. and adapted for use 1
in COEN 180. These notes are intended for clarification of physical data recording mechanisms
in some basic technologies and are not intended for critical review as with the readings drawn
from the research literature used in the rest of the course.
!
Figure 1: Storage Transistor with Floating Gate.
The floating gate is completely su
ounded by an isolation layer. This enables the
floating gate transistor to be used as non-volatile memory, but also imposes the
need to find ways to charge or discharge it.
In a FAMOST (floating gate avalanche injection MOS transistor), the isolation
layer is impermeable only to low energy electrons, but can be passed by high
energy electrons. A pulse of about 20V is applied between the word line and the bit
line (control gate and drain) for about 50ms. This accumulates in the channel
egion between drain and sink hot (fast) charge ca
iers, that have enough energy to
pass the isolation region between the substrate and the floating gate. This
accumulates a charge on the floating gate. We cannot reverse the voltage in order
to remove the charge from the floating gate. To erase the charge, this type of
transistor is subjected to UV radiation which in a few minutes is abso
ed by most
of the charge ca
iers in the floating gate. They have sufficiently high energy to
escape through the insulation layer.
This type of device is used in so-called EPROM (erasable programmable read only
memory). For writing, an EPROM programmer is available. For erasure, an
EPROM chip has a quartz window, through which UV radiation can be applied.
The next generation of floating gate transistors use a thin layer of gate oxide
etween the floating gate and the channel region of the substrate. Charging the
floating gate is done by the same method, a 50ms long 20V pulse that draws
electrons from the channel region through the thin layer of gate oxide into the
floating gate. For discharging, we can now apply an inverse voltage of 20V, that
moves the charge from the floating gate into the channel region. If we were to
apply the inverse voltage for too long, then we would move electrons from the
control gate into the floating gate, hence, we do not do that.
Flash memory is built from floating gate transistors without a different
programming / erasure voltage. Several main mechanisms are available to move
charge ca
iers through the tunnel oxide layer, namely Polyoxide Conduction,
CHEI (Channel hot electron injection) and the high electric field Fowler-Nordheim
tunneling.
Fowler-Nordheim tunneling is a quantum-mechanical process in which a particle
can pass through a classically (as in pre-quantum mechanics physics) fo
idden
egion. To make use of the Fowler-Nordheim effect, we need to apply a strong
injection field acorss the oxide. The strength of the field can be achieved by either
thin oxide layers (so that the voltage can remain small), or by using oxides grown
from polycrystalline silicon (which have a rough surface that leads to electric field
variations and hence enhanced tunneling of the electrons). An alternative (CHEI)
to tunneling is providing electrons with high energy to pass from the channel into
the floating gate. This implies providing a high voltage differential between the
drain and the control gate. Cu
ent flash memories use either FN tunneling
(involving the construction of thin oxide layers) or use hot electron insertion
(involving a higher voltage of e.g. 5-20V).
Increasing the number of programming-erasing cycles and the density of flash
memory remain flash memory design challenges.
A
ay Designs
Flash memory a
ays strive for a very compact layout. A large variety of different
designs, using either F-N or CHE for programming, have arisen, and compete at
the market place. Read access is done rapidly using conventual circuitry for access
and readout. However, erasure and writing are very slow operations. To overcome
these limitations, flash memories are subdivided into blocks, allowing erasing and
writing to be done at the block level. Erasure is usually performed for a complete
lock, hence the name "flash". Internal registers and buffers provide temporary
storage for pages of data. A charge pump circuit is required to provide the high
internal voltages needed for erase and write operations.
!
Figure 2: NOR a
ay layout of flash memory. (SL source lines, (BL bit lines, WL
word lines)
Figure 2 gives a basic "NOR a
ay" a
angement for flash memory. To read a cell,
we assert a single word line. The source lines are asserted and the assertion or
deassertion of a bit line gives the contents of the storage cells in the same row.
Figure 3 gives the principal possibilities of erasing a NOR cell as well as the
principal method of writing it.
!
Figure 3: NOR cell erasure methods and program methods:
( Upper Left High Voltage Source Erase, Upper Right: Negative Gate Source
Erase, Lower Left: Channel Erase, Lower Right: Programming)
The NAND