Solution
Robert answered on
Dec 23 2021
PROJECT REPORT
Title: Ripple Ca
y Adder Circuits: Design and analysis
Objective:
The main objective of this lab is to explore the design space for combinational digital designs
(Ripple ca
y Adder) and to become familiar with the Xilinx ISE synthesis environment. In this,
synthesis of Ripple ca
y adder will be performed and then synthesis report will be studied
and summarized here with relevant data. This project deals with the design and analysis of
16-Bit Ripple Ca
y Adder (RCA) and is simulated in Xilinx. Worst case Propagation Delay is
found and different approach of reduction of WPD is analysed and a suitable technique is
opted. The speed Vs area graph is plotted and graph is further analysed for the conclusion.
Introduction:
In this report we will investigate the synthesis aspect of design. For better understanding of
the digital design flow, Let us first explore the ASIC Design flow.
The ASIC Design Flow is given by:
Specification
▼
RTL Coding and Simulation
▼
Logic Synthesis
▼
Optimization
▼
Gate Level Simulation
▼
Static Timing Analysis
▼
Place and Route
▼
Static Timing Analysis
Procedure:
1.Create a new project the same way you did in Lab 1. Instead of simulating the design, we
will synthesize the design. To synthesize the design circuit (rca.vhd) go through the following
steps:
a. First, create a new project using the Xilinx ISE tool. Double click the ISE Design button on
the desktop and Select the New Project button in the upper left corner.
. Change the Location from “C:\Users” to “C:\Lab1”, then give the project a descriptive
Name like L1_RCA, and then select Next.
c. In the project settings box, change the Family to Virtex6, the Device to XC6VLX240T, the
Package to FF1156, and the speed grade to -1, and then select Next. On the next screen
select Finish.
d. To add the source code to the new project, select Project → Add Source along the top
menu; in the C:\lab1 directory, highlight the rca.vhd and tb_rca.vhd files then hit open;
under the Association column select Simulation for the test bench file, tb_rca.vhd; and
finally select OK.
e. To run the synthesis tool, select the Implementation button in the upper left corner and
highlight the design code (rca.vhd). Note: do not double-click the rca.vhd file!
f. In the lower window, RIGHT click the Design utilities button.
g. In the pop-up window, select the “Design Goals and Strategies” button.
h. In the new pop-up window, you can select from several synthesis options for your design:
Balanced, Area Reduction, Power, and Timing Performance. For this lab, we will use a
“Balanced Approach,” so just hit OK.
i. Next, right click the “–” button next to the “User Constraints” tab. This provides access to
the menu where we can assign specific timing constraints and FPGA pins.
j. To complete the synthesis for this lab, double-click the “Generate Programming File”
utton.
k. After synthesis is complete, the design summary shows in the right hand window.
Additionally, there are several other reports available for your perusal. Click around to see
what’s available.
Results:
Ripple ca
y Adder Synthesis Report:
Device Utilization Summary [-]
Slice Logic Utilization Used Available Utilization Note(s)
Number of Slice Registers 0 93,120 0%
Number of Slice LUTs 16 46,560 1%
Number used as logic 16 46,560 1%
Number using O6 output only 8
Number using O5 output only 0
Number using O5 and O6 8
Number used as ROM 0
Number used as Memory 0 16,720 0%
Number used exclusively as route-thrus 0
Number of occupied Slices 11 11,640 1%
Number of LUT Flip Flop pairs used 16
Number with an unused Flip Flop 16 16 100%
Number with an unused LUT 0 16 0%
Number of fully used LUT-FF pairs 0 16 0%
?&ExpandedTable=DeviceUtilizationSummary
Number of slice register sites lost
to control set restrictions
0 93,120 0%
Number of bonded IOBs 50 360 13%
Number of RAMB36E1/FIFO36E1s 0 156 0%
Number of RAMB18E1/FIFO18E1s 0 312 0%
Number of BUFG/BUFGCTRLs 0 32 0%
Number of ILOGICE1/ISERDESE1s 0 360 0%
Number of OLOGICE1/OSERDESE1s 0 360 0%
Number of BSCANs 0 4 0%
Number of BUFHCEs 0 72 0%
Number of BUFOs 0 18 0%
Number of BUFIODQSs 0 36 0%
Number of BUFRs 0 18 0%
Number of CAPTUREs 0 1 0%
Number of DSP48E1s 0 288 0%
Number of EFUSE_USRs 0 1 0%
Number of GTXE1s 0 12 0%
Number of...