The circuit of Fig. P6.13a contains a JK flip-flop and a D flip-flop. Complete the timing diagram of Fig. P6.13b by drawing the waveforms of signals Q1. and Q2, assuming that:
(a) The 1K flip-flop is negative edge triggered.
(b) The 1K flip-flop has data lockout.
Â
Already registered? Login
Not Account? Sign up
Enter your email address to reset your password
Back to Login? Click here