Question 31) Design a MOD-5 rising edge triggered asynchronous ripple counter usingJK flip flops.2)...

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Question 31) Design a MOD-5 rising edge triggered asynchronous ripple counter usingJK flip flops.2) Draw the timing diagram showing the waveform output of all the statesof the counter3) If the maximum frequency at which the counter can operate is 33.3M Hz and all the flipflops in the counter have the same propagation time delaytpd, what is the propagation time delay of each flipflop correct to the nearest Nano second. 4) Using full adders, design a binary ripple carry adder for adding binarynumbers of 2-bit words. Draw the logic circuit for the designed adder:
	
Document Preview: Question 31) Design a MOD-5 rising edge triggered asynchronous ripple counter usingJK flip flops.2) Draw the timing diagram showing the waveform output of all the statesof the counter3) If the maximum frequency at which the counter can operate is 33.3M Hz and all the flipflops in the counter have the same propagation time delay tpd, what is the propagation time delay of each flipflop correct to  the nearest Nano second.  4) Using full adders, design a binary ripple carry adder for adding binarynumbers of 2-bit words.  Draw the logic circuit for the designed adder:

David · Accepted Answer

Answer 2. 
F= ABC+(BC+BC)(A’B+AC’)
(i) SOP Form 
Expanding RHS, we have, 
F=ABC+BC(A’B+AC’) 
F=ABC+A’BC+ABCC’ 
F=ABC+A’BC 
F=BC(A+A’) 
F=BC
(ii) F=(B’+C’)’ 
 
(iii)
A B C F=BC 
0 0 0 0 
0 0 1 0 
0 1 0 0 
0 1 1 1 
1 0 0 0 
1 0 1 0 
1 1 0 0 
1            1 1 1
Answer 3.

Question 3 1) Design a MOD-5 rising edge triggered asynchronous ripple counter using JK flip flops. 2) Draw the timing diagram showing the waveform output of all the states of the counter 3) If the...

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