Name EE3312 Final Project December 1, 2020 Project is Due Dec 8, 2020 by 5 AM CST. All work should be submitted as a zip file containing a PDF with the detailed report showing your design and analysis...

Name EE3312 Final Project December 1, 2020 Project is Due Dec 8, 2020 by 5 AM CST. All work should be submitted as a zip file containing a PDF with the detailed report showing your design and analysis (with narratives), Spice screen shots showing the performance and detailed comparison of the design to simulation and a discussion of the results. The zip file should also contain the Spice simulation input files. That means the zip file should only contain 4 files (1 PDF and 3 Spice input files). Grading will be based upon completeness and presentation of written analysis and comparison with simulations. Upload your zip file to Blackboard. 1) Design a differential amplifier using 2n2222 transistors. Use a current mirror to bias the amplifier at a level of your age times 0.1mA. Use Vcc and Vdd of +-15V. Set the bias such that V+ and Vare at 7V quiescent. Set the load resistor to 20 times the age in days you are (from today). Set the differential gain Vod/Vid using Re’s to the month you were born times 3 plus 20. Show all design assumptions, justifications and calculations and compare your design with a Spice simulation. Using a circuit simulator, plot Vid vs Vod and display the bias values to verify calculations to simulation. Calculate the CMRR of your amplifier and verify using circuit simulator (remember the compliance range of your amplifier design and limit input Vid accordingly). 2) Design and simulate a Wien-bridge oscillator using a two stage BJT (2n2907) amplifier with a center frequency of 3 times your age in days (from today). Be sure to include the input resistance of the amplifier into your resistor value calculations. The transistor input capacitance should be small compared to the external capacitors. Show all design equations, justifications and calculations and compare your design with a Spice simulation. Plot the transient output using a circuit simulator and take the FFT to verify your calculations. 3) Design and simulate an LC matching network that will match a load equal to your age in months at a frequency of your age in days squared to a source resistance of the month you were born plus 10. Show all design equations, justifications and calculations and compare your design with a Spice simulation. Show all design equations, justifications and calculations and compare your design with a Spice simulation. Using a circuit simulator, plot Vo/Vin as a function of frequency. Verify your design calculations of the matching bandwidth using this plot. Verify “power in equals power out” of the matching network. Verify voltage gain matches calculated.