1) Find the worst-case and best-case Elmore (parasitic and effort) rising and falling delays of an N-input NOR gate (tpdr, tpdf, tcdr and tcdf) as a function of parameter N. Assume shared contacted...

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1) Find the worst-case and best-case Elmore (parasitic and effort) rising and falling delays of an N-input NOR gate (tpdr, tpdf, tcdr and tcdf) as a function of parameter N. Assume shared contacted diffusion of series PMOS transistors and a fanout of h. Please show RC model and detailed analysis for each case.
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Consider a 3-input (A, B, C) XNOR logic:
a. Write out the logic function.
. Sketch a transistor-level schematic with transistor widths to achieve equal rise and fall resistance equal to that of a unit inverter. Assume that you have both the true and complementary versions of the inputs available. Please use no more than 8 NMOS and 8 PMOS transistors in your schematic.
c. Compute the logical effort of each input and parasitic delay of the 3-input XNOR gate you designed. You can combine each true and complementary as one input in calculating logical effort. Please show detailed analysis.
5) Sketch a 3-input HI-skew NOR gate with degree of skewing of 4 and a 3-input LO-skew NAND gate with degree of skewing of 3. Compute gu, gd, gavg of each gate and compare with logical efforts of unskewed NOR3 and NAND3 gates.
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Answered Same Day Feb 26, 2021

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Pulkit answered on Feb 27 2021

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1) Find the worst-case and best-case Elmore (parasitic and effort) rising and falling delays of an N-input NOR gate (tpdr, tpdf, tcdr and tcdf) as a function of parameter N. Assume shared contacted...

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