ECE347_HW9_Resets_and_Inte
upts
ECE347 Resets and Inte
upts Practice Work
PI = 3
1. Write the code needed to set the normal reset vector to the location called START.
2. Write the code needed to enable the clock monitor reset, and set the COP timer to
about 65 ms, assuming a 4MHz oscillator clock.
3. Write the code to initialize the vectors for the COP and clock monitor.
4. Write the instructions needed in the MAIN BACKGROUND LOOP that reset the COP
timer.
5. Write the inte
upt service routines for COP and clock monitor to behave as
described in the following P-code:
COP inte
upt: ERROR_CODE = $32
XXXXXXXXXXCOP_LOOP GOTO COP_LOOP
Clock monitor inte
upt: ERROR_CODE = $47
XXXXXXXXXXCM_LOOP GOTO CM_LOOP
M_09_Lecture_01_Resets_Inte
upts
ECE347 Module 9 Lecture 1
Resets and Inte
upts
1
Module 9 Lecture 1 Objectives
In this lecture, you will learn:
• What a reset is and how to initialize the reset vectors
• How the COP and clock monitor systems operate
• What an inte
upt is and how it works
• All of the HC12 inte
upt sources
• How to program for inte
upts
• Operating modes of the HC12
2
What is an inte
upt?
A special event (external or internal)
that forces the CPU to divert from the
main program and perform some
service related to the event. Examples
of inte
upt sources include external
switch press, internal timer time-out,
data received from the serial port, etc.
The code that runs during an inte
upt
is called an inte
upt service routine, or
ISR.
LOOPMAIN Inte
uptService
Routine
Functions of Inte
upts
- Coordinating I/O activities such as receiving or transmitting data
- Providing a way to gracefully exit from e
ors and warn users of problems
- Alerting the CPU to perform routine tasks such as battery check
Inte
upt Maskability
- Inte
upts that can be ignored by the CPU are called maskable inte
upts.
- Inte
upts that can’t be ignored by the CPU are called nonmaskable inte
upts.
Inte
upt Programming
There are several things that the programmer must do to incorporate inte
upt code:
Allocate stack space
Initialize the inte
upt vector - see next slide
Initialize the stack pointe
Configure the inte
upt operation
Enable GLOBAL inte
upt flag (CLI)
Enable LOCAL inte
upt flag (source dependent)
Write the inte
upt service routine
nonmaskable
maskable
default
priority
level
lowest
highest
Inte
upt priority
The priority is the order in which the CPU will service inte
upts when several inte
upts
occur at the same time.
The priority on the HC12 is from top down on the list of vector addresses. Resets have
highest priority, followed by nonmaskable inte
upts, followed by maskable inte
upts.
An inte
upt’s priority may be raised to the top of the maskable list by programmng the
HPRIO register to contain that source’s low byte vector address. For example, to make
TIMER CHANNEL 1 the highest maskable priority, one would use:
LDAA #$EC
STAA HPRIO
Resets
Resets are similar to inte
upts in that the flow of code execution is changed. In a reset,
however, the main code is stopped, and the code BEGINS a program execution starting
at the location specified in the vector.
There are two normal resets, power off/on, and the reset pin. Both of these use the same vector,
which is at the top of the list: $FFFE and $FFFF. The code MAIN address should be initialized within
this vector as follows:
ORG $FFFE
FDB MAIN ; make sure MAIN code uses this label
This code initializes the normal reset vector, so after power up or reset switch press,
the normal code will run.
Resets
There are two abnormal resets, clock monitor fail (CLKMON), and COP timeout.
Clock monitor fail means that either the oscillator crystal is bad, or the MCU XTAL pin
input is bad. In either case, the code won’t run right and the user should be notified
of a HARDWARE e
or. Generally, we write code to respond to CLKMON fail by issuing
an e
or warning, then staying in an infinite trap loop. As with the normal reset, we also
need to initialize the vector. Here’s the vector init code:
ORG $FFFC
FDB CM_FAIL ; make sure clock monitor code uses this label
And the e
or handling code might look like this:
ORG $C500
CM_FAIL LDAA #1
STAA HW_FLAG ; set HW bad indicator for use
CM_TRAP NOP
BRA CM_TRAP
Resets
COP stands for Computer Operating Properly and is another name for “watchdog timer.”
The idea here is a timer is set that should not time out for normal code operation. If it does time
out, it means there is a serious SOFTWARE e
or. Again, the user should be notified of a the problem
in a similar manner as before, that is, we write code to respond to COP fail by issuing an e
or warning,
then staying in an infinite trap loop. Here’s the vector init code for COP timeout:
ORG $FFFA
FDB COP_FAIL ; make sure COP code uses this label
And the e
or handling code might look like this:
ORG $C600
COP_FAIL LDAA #1
STAA SW_FLAG ; set SW bad indicator for use
COP_TRAP NOP
BRA COP_TRAP
Resets
Unlike a normal reset, COP and CLKMON must be enabled and configured. This is done using the
COPCTL register and the values in the table below. The CME bit ( b7 = 1) turns on CLKMON. The
set of bits CR2, CR1, CR0 set the time out time for the COP timer.
Table 6.2 COP watchdog rates (RTBYP = 0)
CR2 CR1 CR0
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
Divide E by
off
213
215
217
219
221
222
223
At E = 4.0 MHz
timeout
0 to 2.048 ms
At E = 8.0 MHz
timeout
0 to 1.024 ms
off
2.048 ms
8.192 ms
32.768 ms
XXXXXXXXXXms
XXXXXXXXXXms
1.048 s
2.097 s
off
1.024 ms
4.096 ms
16.384 ms
65.536 ms
XXXXXXXXXXms
XXXXXXXXXXms
XXXXXXXXXXs
COP Timer Reset
One more thing...
The COP timer needs to be reset each time through the main code loop. This is done using the COPRST
egister. Within the main loop, the code for resetting the COP timer looks like this:
...in main loop LDAA #$55
STAA COPRST
LDAA #$AA
STAA COPRST
Example 1.
Write a code segment that initializes the normal reset vector, clock monitor vector, and
the COP vector. The code should also enable CLKMON and COP, and set the COP time
out to about 8ms for an oscillator clock of 8MHz. The main loop of the code should
eset the COP timer, and e
or traps should be written for CLKMON and COP.
Solution to be done in Code Wa
ior.
14
Solution
; Reg Defs
COPCTL EQU $003C
ARMCOP EQU $003F
; vector init
ORG $FFFE
FDB MAIN ; Normal reset vector init
ORG $FFFC
FDB CM_FAIL ; failed CLKMON vector init
ORG $FFFA
FDB COP_FAIL ; failed COP vector init
; Stack Allocation
ORG $1000
STKTOP RMB 10
STKBTM RMB 1
continued...
15
; Normal code
ORG $C000
MAIN SEI ; mask all ints
LDS #STKBTM ; SP init
LDAA #$82 ; % XXXXXXXXXX, CR2-1-0 = 010 for 8ms timeout, FreqE = 4MHz
STAA COPCTL
CLI ; unmask ints = enable GLOBAL int flag
NOP
BG_LOOP NOP
NOP
LDAA #$55 ;
STAA ARMCOP ;
LDAA #$AA ;
STAA ARMCOP ; reset COP timer
NOP
NOP
BRA BG_LOOP
continued...
16
; reset traps
ORG $C200
CM_FAIL NOP
BRA CM_FAIL
ORG $C300
COP_FAIL NOP
BRA COP_FAIL
Note that the simulato
debugger by default turns off COP and CLKMON. This
makes total sense because any
eaks or steps would immediately result in a time
out. Thus, it is challenging to debug code that is related to COP and CLKMON.
Inte
upt Programming - reminde
There are several things that the programmer must do to incorporate inte
upt code:
Allocate stack space
Initialize the inte
upt vecto
Initialize the stack pointe
Configure the inte
upt operation
Enable GLOBAL inte
upt flag (CLI)
Enable LOCAL inte
upt flag (source dependent)
Write the inte
upt service routine
IRQN – external inte
upt pin
The IRQN or IRQ-not (the “not” meaning active low) is available on the HC12 to allow a switch
press to cause an inte
upt. This inte
upt source has an associated configuration register
called INTCR, which allows for edge/level detect (bit 7, edge = 1), enable (bit 6 = 1), and delay
(bit 5 = 1) functions as shown in the image below. The edge/level selection allows for setting
the desired switch operation. Enable turns the inte
upt on – this is the LOCAL enable
it. DLY is used to delay the inte
upt from being active for a few moments during system
start up.
Example 2.
Write a MAIN code segment that initializes the IRQN vector, and enables IRQN with edge
triggering. Also write an IRQN ISR that increments a counter each time it runs.
The solution should be done in Code Wa
ior and observed using the debugger on
eal hardware. In order to do this, one needs to connect the IRQN pin to a pulled up
switch. This is described in detail in the demo lab documentation.
20
Solution
; vectors init
ORG $FFFE
FDB MAIN ; normal reset vecto
ORG $FFF2
FDB IRQN_ISR ; IRQN vecto
; stack allocation
ORG $1000
STKTOP RMB 10
STKBTM RMB 1
IRQ_COUNT RMB 1
; register defs
INTCR EQU $001E
continued...
21
; main code
;
ORG $C000
MAIN SEI
LDS #STKBTM ; SP init
LDAA #% XXXXXXXXXX ; IRQN edge triggered, enabled
STAA INTCR ; store to IRQ control register
CLR IRQ_COUNT ; count = 0 at start up
CLI ; clear int mask = enable global ints
NOP
BG_LOOP NOP
NOP ; do important background stuff here
NOP
BRA BG_LOOP
continued...
22
; inte
upt service routine
;
ORG $C500
IRQN_ISR NOP
NOP
INC IRQ_COUNT ; count = count + 1
NOP
NOP
RTI ; return to main
Note that the simulato
debugger does not work for inte
upts. You will need
to run this code in some real HC12 hardware to observe its operation.
What the MCU does during an inte
upt
The previous example illustrated all the things the programmer must do to make inte
upts
work. The CPU also does quite a few things (automatically) which are interesting to note.
Here are the things that occur in the MCU after an inte
upt trigger is detected:
0. Finish the cu
ent instruction
1. Save all registers (except SP) on the stack
2. Identify cause of trigge
3. Get vector contents (ISR address) from appropriate vecto
4. Execute ISR until RTI is executed
5. Restore all registers (except SP) from the stack
6. Resume MAIN loop execution
Since inte
upts cause all registers to be stacked, this means the stack size needs to be
igger if you’re using inte
upts.
Register Stacking Orde
The registers get pushed onto the stack in the order shown below.
Symbol Data
STKTOP
CCR
A
B
X Hi
X Lo
Y Hi
Y Lo
RTN Hi
RTN Lo
STKBTM --
Operating Modes
The HC12 has several different operating modes. Some modes are for saving battery life, others are
for background debug mode, others are for changing the size of the default data bus. These modes
are controlled according to the table below, or by incorporating special instructions in the code,
such as STOP and WAIT.
When a WAIT is executed: All registers are stacked. CPU clock is stopped. Peripheral clocks continue run.
An internal inte
upt can wake up the CPU. This is “doze” mode.
When a STOP is executed: All registers are stacked. All clocks are stopped. An external inte
upt (switch
press) is needed to wake up the CPU. This is “deep sleep” mode.
Table 6.5 68HC12 Mode Selection
BKGD MODB MODA Mode
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
Special single chip
Special expanded na
ow
Special peripheral
Special expanded wide
Normal single chip
Normal expanded na
ow
Reserved (forced to peripheral)
Normal expanded wide
Port A
general-purpose I/O
ADDR[15:8]DATA[7:0]
ADDR/DATA
ADDR/DATA
General-purpose I/O
ADDR[15:8]DATA[7:0]
--
ADDR/DATA
Port B
general-purpose I/O
ADDR[7:0]
ADDR/DATA
ADDR/DATA
General-purpose I/O
ADDR[7:0]
--
ADDR/DATA
Module 9 Lecture 1 Summary
In this lecture, you have learned:
• What a reset is and how to initialize the reset vectors
• How the COP and clock monitor systems operate
• What an inte
upt is and how it works
• All of the HC12 inte
upt sources, particularly IRQN
• How to program for inte
upts
• Operating modes of the HC12 and STOP/WAIT operation
26