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ECE 3421 Lab 4
Cadence Layout Tools
This lab introduces Cadence layout tools and guides you through the layout process with the
example of a CMOS inverter design in AMI 0.6μm technology. You also need to layout a NOR
gate to finish the homework.
1. Cadence Layout Tool and the Settings
1) Copy the design rule files to your design folder. Open the File Brower in the VM, navigate to
the techfile folder by this path:
Other_Location/Compute
opt/Cadence/CDK/ncsu_cdk/techfile. Then, copy divaDRC.rul,
divaEXT.rul, and divaLVS.rul these three files to the run_cadence folder in your Home
folder. They will be used as the design rules for the DRC (Design Rule Check), Extraction
(EXT), and LVS (Layout Versus Schematic) operations in the layout design.
2) In the Virtuoso windows, go to Tools âž” Technology File Manager and a Technology Tool
Box window will appear as in Figure 1. Click Attach and a Technology Li
ary window will
appear as in Figure 2. Choose the ECE3421 as the Design Li
ary and the
NCSU_TechLib_ami06 as the Technology Li
ary.
Figure 1.
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Figure 2.
3) In the Virtuoso window, go to File âž” New âž” Cellview and a New File window will appear
as in Figure 3. Choose the Li
ary Name as ECE3421, and input Cell Name to INV, and
choose Layout (XL) as the Type, and the View filed will be automatically added as layout.
Click OK to continue, both the Virtuoso Schematic Editing window and the Virtuoso Layout
XL Editing Window will pop-up together as in Figure 4. Ignore any license notifications.
Figure 3.
4) In the Virtuoso Layout Suite XL Editing window, go to Option âž” Display set in the Display
Options window as in Figure 5. Note that setting the Grid Controls setting properly can
make the layout design environment much more convenient. To set as in Figure 5, the
layout would always on grids and the grid spacing is λ (0.3um), which allows us to
create the shapes and know their dimensions by counting the grids they span.
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Figure 4.
Figure 5.
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2. CMOS Inverter Layout Example
There are many steps we need to complete for a successful layout design, but it will become much
easier if we could understand the design and verification flow. In this example, we place rectangles
in various layers to build the NMOS transistor, PMOS transistor, and interconnections. To make
sure our layouts follow the design rules, we would need to refer to the MOSIS design rules (check
HuskyCT). By running DRC and checking our design periodically, we can ensure that we are
conforming to the design rules. After the design is finished and passed DRC, we can extract the
layout design. After passing the LVS check, we can ensure that the extracted layout matches the
schematic.
Let’s start the inverter layout design with the NMOS transistor.
1) Draw the N-diffusion (Active)
First, select the active layer from the LSW (Layer Selection Window) in the left panel of the
Virtuoso Layout Suite XL Editing window as in Figure 6. Then, go to Create âž” Shape âž”
Rectangle (Hotkey R) in the Virtuoso Layout Suite XL Editing window, draw a 6λ x 12λ
ectangle as shown in Figure 7. Here we assume you have enabled the grid to 0.3um (λ) as in the
last section. Since the default NMOS is with 1.5um (5λ) width and 0.6um (2λ) length, the N
active should be therefore 5 grids in vertical to make them match.
Always pay attention to the size of the rectangles that you create. You can also change the exact
size and position after placement by right-clicking at the rectangle and change them in the
Properties. Keep the INV schematic open, when you need to make the comparisons. You may
change your schematic later to make them match too.
Figure 6.
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Figure 7. N-diffusion (active) Rectangle.
You should also periodically do a DRC check to make sure that you are conforming to the
design rules. The DRC check before completion is mainly to make sure the sizing and
spacing you have accomplished are co
ect to ensure the design efficiency. Continue the
design when DRC only reports e
ors or warnings about the part that you haven’t finished.
To run DRC, go to Verify âž” DRC and set the DRC window like Figure 8. As we set
divaDRC.rul as the Rules File, uncheck the Rules Li
ary.
Figure 8.
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2) Draw the Gate Poly
Select the poly layer from the LSW window, and go to Create âž” Shape âž” Rectangle in the
Virtuoso Layout Suite XL Editing window. Draw the gate in a width of 2 λ as in Figure 9.
Figure 9. Gate Poly Rectangle.
3) Make Active Contacts
Select the cc layer from the LSW window, go to Create âž” Shape âž” Rectangle in the Virtuoso
Layout Suite XL Editing window. Draw two contact squares as in Figure 10. The contacts must
e exactly 0.6um by 0.6um (2λ x 2λ).
Figure 10. Active Contacts.
4) Cover Contacts with Metal 1
Select the metal 1 layer from the LSW window, and go to Create âž” Shape âž” Rectangle in the
Virtuoso Layout Suite XL Editing window. Draw two metal 1 rectangles (4λ x 6λ) to cover the
contacts as in Figure 11.
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Figure 11. NMOS layout.
5) Draw Nselect
Select the nselect layer from the LSW window, and go to Create âž” Shape âž” Rectangle in the
Virtuoso Layout Suite XL Editing window. Draw a rectangle extending over the active region by
0.6μm (2λ) in all directions as in Figure 12.
Now we have finished the layout of an NMOS transistor. Next, we will draw a PMOS transistor.
Figure 12. NMOS layout.
6) Repeat the steps 1)-5) to draw a PMOS transistor
Use the pselect layer instead of the nselect layer. You should end up with a layout as in Figure
13, in which the PMOS transistor is above the NMOS transistor.
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Figure 13. The Layout of PMOS.
7) Draw the N-Well
Select the nwel1 layer from the LSW window, draw an N-Well rectangle as in Figure 14.
Figure 14. The Layout of NMOS and PMOS transistors.
So far, we have finished the layout of the NMOS and PMOS.
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