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ECE 730 final Project: due Dec 15th 4pm (Late submission: 20% reduction for every 24 hours delay) Your task is to analyze and design both the converters shown in Fig. 1. The topology and modulation...

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ECE 730 final Project: due Dec 15th 4pm
(Late submission: 20% reduction for every 24 hours delay)
Your task is to analyze and design both the converters shown in Fig. 1. The topology and modulation scheme are shown in
Fig. 1 and Fig. 2. (Please note that considering the magnetizing inductance of the transformer is necessary for converter
analysis and design)
S4
S3
S1
S2
Vin RLC
+
Vo
-
L
n
1
1
D1
D2

(a)
S4
S3
S1
S2
Vin
RLCL
n
1
1
D1
D2
+
Vo
-

(b)
Figure 1. Topology of the Full Bridge Converter. (a) configuration 1. (b) configuration 2.
VGS1&VGS3
VGS2 &VGS4
t
t
T
T/2
D.T
D.T

Figure 2. Modulation Scheme
ECE 730 final Project: due Dec 15th 4pm
(Late submission: 20% reduction for every 24 hours delay)
I. ANALYSIS:
1. At each interval determine the switches that are conducting.
2. Assuming DC capacitor voltage and DC cu
ent for filter inductance L, draw the following waveforms:
a. Transformer primary voltage
. Magnetizing inductance cu
ent
c. Voltage across the inductor L
d. Voltage and cu
ent of the switches (S1, …, S4, D1, D2)
3. Obtain voltage conversion ratios and cu
ent conversion ratios.
4. Using the waveforms in (3), find the peak voltage and cu
ent for all switches.
5. Using the waveforms in (3) and neglecting the magnetizing cu
ent (ILm), calculate the RMS cu
ent of MOSFET (Is), all
transformer windings (I1, I2, I3), inductor L, and the average cu
ent of the diodes.
7. Calculate the cu
ent ripple of magnetizing inductance Lm, and inductor L, and the voltage ripple of capacitor.
II. IDEAL CONVERTER DESIGN:
Consider all the components are lossless, design the converters to achieve the following specs:
Vin=44V (fixed), Vo(nominal)=22V, Vo(min)=11V, Vo(max)=33V, Po=100-200W, fsw=50KHz, Vo(max ripple)=1%, IL(max
ipple @ Po=200W)=50%, @?o = 200?, iLm(max)≤ 0.1?1(max).
1. Assume the maximum duty cycle is D=0.5 and find the transformers turns ratio.
2. Calculate the minimum and nominal duty cycles.
3. Using the cu
ent and voltage ripple equations, determine the operating points (Vin and Po) that result in largest cu
ent
ipple and voltage ripple for Lm, inductor L, and capacitor.
4. Determine the values of Lm, inductor L, and capacitor to ensure @? = 200?, iLm(max) ≤ 0.1 I1, IL(max ripple @
Po=200W)=50%, and Vo(max ripple)=1%.
5. Using the obtained switches’ peak cu
ent and voltage, determine the operating points (Vin and Po) that result in largest
cu
ent stress for each switch and the operating points that results in largest voltage stress for each switch.
6. Select MOSFET and diode that can tolerate at least 125% of the calculated voltage and cu
ent stress.
III. Lossy Converter Design:
Consider converter switches and passive components dissipate a portion of the input power such that ?o/Pin = ?, (? < 1).
1. Does this situation change the converters cu
ent conversion ratio? (Neglect the magnetizing cu
ents and justify your
esponse)
2. Using the response to section III.1 and ?o/Pin=0.9 (90% efficiency), calculate the voltage conversion ratio for the lossy
converters.
Now consider the design problem stated in II. Ideal Converter Design and design the lossy converter in the following steps.
ECE 730 final Project: due Dec 15th 4pm
(Late submission: 20% reduction for every 24 hours delay)
3. Assume that the maximum duty cycle is limited to D=0.45 due to the dead time effects, and then find the transformer
turns ratio.
4. Calculate the minimum and nominal duty cycles for both converters.
5. Determine the values of Lm, inductor L, and capacitor to ensure @? = 200?, iLm(max) ≤ 0.1 I1, IL(max ripple @
Po=200W)=50%, and Vo(max ripple)=1%.
6. Make a short list of MOSFETs and diodes that can tolerate at least 125% of the calculated voltage and cu
ent stress.
Select a MOSFET and a diode following these steps:
a. Using the RDS(on) (On state resistance) and Co (Output parasitic capacitance) values for MOSFET and VF (Forward
voltage drop) for the diode, calculate the power loss of each switch for Po=200W and Vo=22V. (ignore the diode’s
switching losses and any revers recovery and assume IG(H-L) and IG(L-H) equal to 2 Amps)
. Calculate Tj using the ??ℎja value and assuming TA=30 C.
c. Check the temperature raise constraint as: Tj < 0.9Tjabsolute
7. Using AAw method determine the operating point (Vin and Po) that results in minimum core size for transformer and
inductor L.
8. Using the opted operating point for each of transformer and inductor L, design the magnetic components.
a. Only use the standard EE type cores and co
esponding bo
ins as provided in the link in notes section.
. Use 3F3 material (0.3T saturation) for your design.
c. Only if ?/? > 1.6, use Litz wire, else use single conductor (d wire diameter, ? skin depth)
d. If you require to use Litz wire use the strand size of AWG28 with d=0.32mm suitable for 50kHz.
e. Assume ρ=2*10-8 ohm*m
f. Use the layer fill factor of at least 0.85 and larger.
g. Always round up the obtained number of turns to next integer in both transformer and inductor (There is no need to
have the exact same turns ratio as calculated for transformer and simply round up the numbers)
9. Calculate the Lm for your designed transformer, check if it satisfies the constraint found in question II.4? If not, what
changes are required (Just explain. No design is required for this section).
10. Find the total core and copper loss of your magnetic components, inductors and transformers.
11. Simulate the converter for both ideal and non-ideal cases and include the results for all operating points. (Use equivalent
parasitic resistance to model the core and conduction losses for the magnetic components and for switching losses)
12. Using the obtained magnetic losses and total switch losses, calculate the efficiency of the converters for different output
powers and input voltages and fill the following table. Are the efficiencies larger than 90%? If not, what are the possible
improvements?
Efficieny of Converter (a) Efficieny of Converter (b)
Calculation Simulation Calculation Simulation
Po=100W and Vo=11V
Po=100W and Vo=22V
Po=150W and Vo=22V
Po=200W and Vo=11V
Po=200W and Vo=22V
Po=200W and Vo=33V
ECE 730 final Project: due Dec 15th 4pm
(Late submission: 20% reduction for every 24 hours delay)
Note:
• The way you write and structure your report is also important. It should be easy to follow and understand.
• The reports must be typed. Handwritten reports won’t be considered for grading.
• Please mention description and details as much as you can. However, don’t forget to highlight the final or important values.
• Please submit simulation source files, datasheets, both word/LATEX and PDF of the assignment and all the related materials.
• Use this link for core and bo
in information: http:
fe
oxcube.home.pl/prod/assets/ecores.htm
Answered 13 days After Dec 05, 2021

Solution

Amar Kumar answered on Dec 14 2021
129 Votes
ECE 730 final Project: due Dec 15th 4pm
(Late submission: 20% reduction for every 24 hours delay)

ECE 730 final Project: due Dec 15th 4pm
(Late submission: 20% reduction for every 24 hours delay)

ECE 730 final Project: due Dec 15th 4pm
(Late submission: 20% reduction for every 24 hours delay)

Your task is to analyze and design both the converters shown in Fig. 1. The topology and modulation scheme are shown in Fig. 1 and Fig. 2. (Please note that considering the magnetizing inductance of the transformer is necessary for converter analysis and design)
(a)
(b)
Figure 1. Topology of the Full Bridge Converter. (a) configuration 1. (b) configuration 2.
D.T
V
GS
1
&
V
GS
3
V
GS
2

&V
GS
4
t
t
T/2
D.T
    T    
Figure 2. Modulation Scheme
    I.     ANALYSIS:

1. At each interval determine the switches that are conducting.
A clamping diode is put across the gatherer producer terminals of every semiconductor, and they are driven on the other hand two by two. For one half-cycle, semiconductors T1 and T3 are empowered together, and for the other half-cycle, semiconductors T2 and T4 are invigorated together. The full-span converter enjoys the benefit of just requiring one capacitor for yield voltage smoothing, though the half-span converter required two.
2. Assuming DC capacitor voltage and DC cu
ent for filter inductance L, draw the following waveforms: a. Transformer primary voltage
. Magnetizing inductance cu
ent
c. Voltage across the inductor L
d. Voltage and cu
ent of the switches (S1, …, S4, D1, D2)
3. Obtain voltage conversion ratios and cu
ent conversion ratios.
4. Using the waveforms in (3), find the peak voltage and cu
ent for all switches.
5. Using the waveforms in (3) and neglecting the magnetizing cu
ent (ILm), calculate the RMS cu
ent of MOSFET (Is), all transformer windings (I1, I2, I3), inductor L, and the average cu
ent of the diodes.
6. Calculate the cu
ent ripple of magnetizing inductance Lm, and inductor L, and the voltage ripple of capacitor.
II.     IDEAL CONVERTER DESIGN:
Consider all the components are lossless, design the converters to achieve the following specs:
Vin=44V (fixed), Vo(nominal)=22V, Vo(min)=11V, Vo(max)=33V, Po=100-200W, fsw=50KHz, Vo(max ripple)=1%, IL(max ripple @ Po=200W)=50%, @?o = 200?, iLm(max)≤ 0.1?1(max).
1. Assume the maximum duty...
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