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1.WITH THE AID OF DIAGRAM, BRIEFLY EXPLAIN HOW COLLECTOR CURRENT IS OBTAIN IF THE TRANSISTOR IS CONNECTED IN C-E CONFIGURATION. 2. HOW IS PHASE REVERSAL ACHIEVED BETWEEN THE INPUT AND OUTPUT IN THE...

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1.WITH THE AID OF DIAGRAM, BRIEFLY EXPLAIN HOW COLLECTOR CURRENT IS OBTAIN IF THE TRANSISTOR IS CONNECTED IN C-E CONFIGURATION.
2. HOW IS PHASE REVERSAL ACHIEVED BETWEEN THE INPUT AND OUTPUT IN THE CIRCUIT?
Answered Same Day Dec 22, 2021

Solution

Robert answered on Dec 22 2021
137 Votes
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TRANSISTOR IS CONNECTED IN C-E CONFIGURATION.
The collector cu
ent versus collector-emitter voltage graph is shown in
figure two. This graph shows the common emitter transistor
characteristics.
The DC bias defines the DC operating point of the transistor. The DC
operating point is also known as the Quiescent Point.
The transistor could be in one of the three states: the active state, the
saturation state or the cut off state.
In the active state the base-emitter junction is forward biased and the base
collector junction is reverse biased. The active region shown in Figure
two gives us collector cu
ent, collector to emitter voltage and base
cu
ent. The DC operating point is in this region for most analog transistor circuits. In figure two, this is the region to the left of the "Vc (sat)"
vertical line and above the horizontal line labeled "Ib = 0."
In the saturation state, the base emitter junction is forward biased and the base collector junction is forward biased. In figure two, this is the
egion to the right of the "Vc (sat)" vertical line. Note that "Vc (sat)" is associated with "Ib (sat)" at the DC load line.
In the cut off state, the base emitter junction is not forward biased and the base collector is reverse biased. The base cu
ent is zero amperes and
consequently no collector cu
ent flows. In figure two, this is the region below the "Ib = 0" horizontal line.
In figure two the diagonal line extending from "Vcc/(R1+R2)" to "Vcc" is the DC load line. The quiescent point is labeled the Q Point in figure
two. Note that the Q point defines the collector-emitter voltage and the collector cu
ent for the circuit in Figure One. Also note that the Quiescent
Point is in the active region.
The point of saturation is dependent on the values of the resistors R1 and R2, and the voltages at the base, emitter and collector of the transistor.
The collector voltage Vc is equal to:
Vc = Vcc - Ic*R1
where Vc is the voltage at the collector of the transistor and
Ic is the collector cu
ent through R1.
HFE is the DC cu
ent gain....
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