Microsoft Word - Final Project
Final Project
In this final project, you will design a sequential arithmetic circuit.
1, Implement the schematic and layout of a static MS register (slide 16 of Lecture 16). Determine
the setup time, hold time, and clock-to-Q delay of the MS register from simulations.
2, Implement the schematic and layout of a full adder (slide 9 of Lecture 18) and connect the
static MS register to the inputs and outputs of the full adder. Ignore clock skews and jitters.
Determine the maximum clock frequency of this sequential circuit. Check for setup time and
hold time failures, if any.
Schematic Design
You should hand in the schematic diagrams of all functional blocks. The transistors need to be
sized properly for a balanced design. Performance measurements such as the longest and shortest
path delays of the full adder, clock-to-Q delay, setup time, hold time of the MS register,
maximum clock frequency of the sequential circuit, and possible setup/hold time failures should
e obtained from simulations.
Layout Design
Layout should match your logic design including the transistor sizes. Layout design is the most
time-consuming part, so start your design ASAP.
Final Project Report
The final report is due by midnight April 29. It should include the schematic design, layout, and
simulation results.
Grading
Completeness: 50
Performance (layout size, register timing, speed): 40
Report writing: 10