1. Draw the circuit represented by the following VHDL process. Use only two gates. Why is clr on...

Question

1. Draw the circuit represented by the following VHDL process. Use only two gates.
Why is clr on the sensitivity list but C is not?
Solution:
Clr signal is in sensitivity list because it is asynchronous input and therefore i
espective of clock position,
the output should become zero as soon as clr signal is set to ‘1’. The impact od signal ‘c’ is visible only at
the falling edge of clock signal and if ‘CE’ Chip Enable signal is ‘1’.
2. (a) Write a selected signal assignment statement to represent the 4-to-1...

Robert · Accepted Answer

1. Draw the circuit represented by the following VHDL process. Use only two gates.
Why is clr on the sensitivity list but C is not?
Solution:
Clr signal is in sensitivity list because it is asynchronous input and therefore irrespective of clock position, 
the output should become zero as soon as clr signal is set to ‘1’.

1. Draw the circuit represented by the following VHDL process. Use only two gates. Why is clr on the sensitivity list but C is not? 2. (a) Write a selected signal assignment statement to represent the...

Solution

Answer To This Question Is Available To Download

Related Questions & Answers

Submit New Assignment