30/10/2019 https:
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CSc 205 Verilog Programming #3: Adder-Subtractor (A
ays of Gates & Modules)
1. In this programming assignment, we will practice the use of modules as an a
ay!
2. Write a Verilog program to simulate a 5-bit adder-subtractor. Submit only 1 program file "add-sub.v" to
your "3rdPrgAssig" folder. (Make a "V2" folder for revision 2, in the same folder to re-submit. Use
"V3" for another revision, and so on.) Misplaced files may get points deducted.
3. A single Full Adder (FA) is illustrated below. Make the final simulated based on a 5-bit adder-
subtractor which will have five FA's chained. The five xor gates are used to flip y bits when performing
a subtraction. The 6th xor gate is used to detect an overflow condition (explained below).
4. The first ca
y-in bit C0 can serve as the flag to perform a subtraction if set 1. If 0, it performs addition.
The truth table shows the s (sum) and cout (ca
y-out)
its are results of a majority function and parity check:
cin x y -> cout s
XXXXXXXXXX
XXXXXXXXXX
XXXXXXXXXX
XXXXXXXXXX
XXXXXXXXXX
XXXXXXXXXX
XXXXXXXXXX
XXXXXXXXXX
Follow the diagram below to program a Full
Adder.
Multi-bit Adder / Subtractor (program an a
ay of full adders)
5. Keyboard Input Examples: how to program for keyboard input.
6. The keyboard input asks for two numbers X and Y. Each ranges from 0 to 15 (by entering '00'to '15').
Afterward, a plus or minus sign ('+' or '-') should be entered to perform either an addition o
subtraction.
7. To copy the demo executable and run it:
atoz[193]% cp -p ~changw/html/205/prg/3/demo-a.out .
atoz[194]% demo-a.out
Enter X (range 00 ~ 15):
10
Enter Y (range 00 ~ 15):
03
Enter '+' or '-':
+
X= XXXXXXXXXXY= XXXXXXXXXXC0=0
Result= XXXXXXXXXXE = 0
atoz[195]% demo-a.out
Enter X (range 00 ~ 15):
12
Enter Y (range 00 ~ 15):
13
Enter '+' or '-':
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-
X= XXXXXXXXXXY= XXXXXXXXXXC0=1
Result= XXXXXXXXXXE = 0
atoz[196]% demo-a.out
Enter X (range 00 ~ 15):
01
Enter Y (range 00 ~ 15):
15
Enter '+' or '-':
-
X= XXXXXXXXXXY= XXXXXXXXXXC0=1
Result= XXXXXXXXXXE = 0
atoz[197]% demo-a.out
Enter X (range 00 ~ 15):
11
Enter Y (range 00 ~ 15):
15
Enter '+' or '-':
+
X= XXXXXXXXXXY= XXXXXXXXXXC0=0
Result= XXXXXXXXXXE = 1
8. The ASCII value obtained from the input must be converted, e.g., if '13' is entered, it gets 49 and 51
(ASCII value), then a subtraction of 48 is needed for each to get the value of 10's and 1's.
9. The xor of the last two ca
ies generates the E indicater. If E is 0, the sum bits are OK as a 2's
complement result. If E is 1, then the final ca
y-out bit is needed to place in front of the result.
Otherwise, the result will not be co
ect in the signed 2's complement bitmap. E is the true overflow
indicator. overflowed.)
10. The skeleton of your program should look like this:
add-sub.v, 205 Verilog Programming Assignment #3
can do both add & subtract on 5-bit operands
use a
ays of gates and modules
PUT YOUR NAME HERE
module TestMod;
parameter PLUS_SIGN = 43;
parameter MINUS_SIGN = 45;
parameter STDIN = 32'h8000_0000;
keyboard input channel
reg [7:0] str [1:3];
typing in, 3 chars
reg [4:0] X, Y;
5-bit X, Y to sum
reg C0;
set 0/1 to do add/subtract
wire [4:0] S;
5-bit Sum to see as result
wire E;
E
or indicator, overflow
instantiate AddSubMod (with input C0, X, and Y, output E and S)
initial begin
XXXXXXXXXXprompt for keyboard entry --> $display("Enter X (range 00~15): ");
XXXXXXXXXXget 1st character --> str[1] = $fgetc(STDIN);
XXXXXXXXXXget 2nd character
XXXXXXXXXXget 3rd character (Enter key)
XXXXXXXXXXconvert from 1st (10's) and 2nd (1's) chars to X
XXXXXXXXXXrepeat above for Y)
XXXXXXXXXXget a char (and the Enter key)
XXXXXXXXXXif it is '+,' set C0 to 0
add X and Y
XXXXXXXXXXotherwise (assume '-'), set C0 to 1
subtract Y from X
XXXXXXXXXX. #2;
wait a bit for the add/sub to get done
XXXXXXXXXXdisplay X, Y, S, and E (see demo runs)
end
endmodule
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module AddSubMod(C0, X, Y, S, E);
input C0;
single bit input
input [4:0] X, Y, ...
4-bit input items
output ...
output ... (multiple output lines due to size differences)
...
...
use ARRAY of gates: xor my5xor [4:0] (...);
and ARRAY of module instances: FullAdderMod my5FA [?:?] (...);
endmodule
module FullAdderMod(...);
single-bit adder module
...
XXXXXXXXXXfollow the diagram)
...
endmodule
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