Microsoft Word - hw4-vhdl
CENG XXXXXXXXXXDigital System Design
Homework 4
Due Date: March 1
In this homework, you will design three components using VHDL. For each problem, you need
to add necessary comments in each source code and provide explanations on the waveforms.
Code Submission Guidelines:
o Each problem in a homework is a Xilinx workspace folder
o Name each workspace folder with a decent name (e.g, hw1_prob1_xor)
o Zip all workspace folders in one zip folder
o Name the zip file in the following format: ceng4354_hwnumber_yourlastname.zip ( e.g.,
ceng4354_hw1_koc.zip)
Problem 1: (30 pts)
Design a 16-bit Arithmetic Unit which consists of one 16-bit adder, 16-bit subtractor, 16-bit
incrementer, and 8-bit multiplier. You can use below entity declaration for your design. The
least-significant 8 bits of A and B are used as inputs of the multiplier. The output will be 16 bits.
The operation of arithmetic unit depends on the value of input Select.
entity ArithmeticUnit16bit is
Port(A : IN std_logic_vector(15 downto 0); -- Input
XXXXXXXXXXB : IN std_logic_vector(15 downto 0); -- Input
XXXXXXXXXXOp_Sel: IN std_logic_vector(1 downto 0);--operation selection
XXXXXXXXXXArithOut: OUT std_logic_vector(15 downto 0); -- Result
XXXXXXXXXXCout : OUT std_logic); --ca
y out bit of operation
end ArithmeticUnit16bit;
Note:
8-bit multiplier has only 16 bits as output, the ca
y out of arithmetic unit must be 0
when a multiplication operation is performed.
The ca
y out of this unit must be 1 after incremental operation is performed when
cu
ent A’s value is 0xFFFF (Overflow case)
For example: if A = 0xFFFF, then A = A + 1 = 0x0000 and ca
y out = 1
The following table describes this unit’s behavior:
Op_Sel(1 downto 0) Operation
00 A * B
01 A + B
10 A – B
11 Increment A ( A +1)
Report : VHDL code and waveforms
CENG XXXXXXXXXXDigital System Design
Problem 2: (20 pts)
Design a 16-bit Shifter unit with A, B, Type and Direction as inputs and ShiftOut as output. The
value of A should be shifted or rotated by the value specified in B. The “Direction” bit is used to
determine whether to shift
otate left(0) or right(1). The “Op_Type” bit is used to determine
whether to Shift(0) or Rotate(1) the data. This 16-bit Shifter has the following entity declaration:
entity ShiftUnit16Bits is
port(A, B : IN std_logic_vector(15 downto 0);
Direction, Op_Type : IN std_logic;
ShiftOut : OUT std_logic_vector(15 downto 0));
end ShiftUnit16Bits;
The “Direction” bit is used to determine whether to shift
otate left (0) or right (1).
The “Op_Type” bit is used to determine whether to shift(0) or rotate(1)
The value of A should be shifted by the value specified in B.
The shifted bits are replaced by 0.
Write a test bench that verifies the functionality of your design; make sure to have all possible
operations of this unit in your test bench.
Below table describes this unit’s behavior:
Op_Type Direction Operation
0 0 Shift Left(A,B)
0 1 Shift Right(A,B)
1 0 Rotate Left(A,B)
1 1 Rotate Right(A,B)
Report : VHDL code and waveforms
CENG XXXXXXXXXXDigital System Design
Problem 3: (20 pts)
Design a 16-bit data memory with Address_DM, Data_In_DM, We_DM, Re_DM and Clock as
inputs and Data_Out_DM as output. When write enable signal We_DM is 1, data memory will
write data Data_In_DM to the address Address_DM at the active clock edge. When read enable
signal Re_DM is 1, data memory will read data from the address Address_DM at the active
clock edge. If both these control signals are 1 at the active clock edge, then write operation will
e performed instead of read operation.
This data memory can hold up to 32 data elements. The size of each data element is 16 bits. This
data memory has the following entity declaration:
entity DataMemory16Bits is
port(Address_DM : IN std_logic_vector(15 downto 0);
Data_In_DM : IN std_logic_vector(15 downto 0);
Clock : IN std_logic;
We_DM, Re_DM : IN std_logic; --write and read enable
Data_Out_DM : OUT std_logic_vector(15 downto 0));
end DataMemory16Bits;
Report : VHDL code and waveforms