Microsoft Word - project-ALU
You have designed and validated various components using VHDL throughout the semester using Xilinx Vivado. In your final VHDL project, you are to design a 16-bit ALU using previously designed components as well as a few new ones. Note that there is no extension for this project and late submissions will get 0. In your report, you need to add necessary comments in each VHDL code (including design and testbench) and provide explanations on the waveforms.
Code Submission Guidelines:
· Each problem in a homework is a Xilinx workspace folder o Name each workspace folder with a decent name (e.g, hw1_prob1_xor)
· Zip all workspace folders in one zip folder
· Name the zip file in the following format: ceng4354_hwnumber_yourlastname.zip (e.g., ceng4354_hw1_koc.zip)
Project Description:
Design the 16-bit Arithmetic Logic Unit (ALU) shown in the figure below. A (16-bit), B (16-bit), Opcode (3-bit), and Mode (1-bit) are the inputs; and ALUOut (16-bit) and Cout (1-bit) are the outputs of the design. A and B hold the values of the operands. Mode and Opcode together indicate the type of the operation performed by ALU.
In your project, you can either use previously developed components or design new ones. However, it is recommended to reuse the components you already designed in previous assignments.
Components:
Design the Arithmetic Unit that consists of one 16-bit adder, 16-bit subtractor, 16-bit incrementer, and 8-bit multiplier. The least-significant eight bits of A and B are used as inputs of the multiplier. The output will be 16-bit. (This unit was designed previously)
Design a 16-bit Logic Unit which performs the following operations: A and B, A or B, A nand B, A nor B, A xor B, A xnor B, Not A and Not B.(This unit was designed previously)
Design a 16-bit Shifter unit with A, B, Type and Direction as inputs and ShiftOut as output. The value of A should be shifted by the value specified in B. The “Direction” bit is used to determine whether to shift left (0) or right (1) and the “Type” bit is used to determine whether to Shift (0) or Rotate (1) the data. (This unit was designed previously)
Design a 16-bit 2-to-1 Multiplexer. The MUXes are utilized in order to route the outputs of functional units to ALU output. (This Multiplexer was designed previously)
Design the controller that is responsible for generating the required control signals for all functional blocks in your design. Select is used to select the functional unit for the co
esponding operation in Arithmetic Unit. Sel1 and Sel2 are utilized as select signals of MUXes. Sel_Cout is used to control the cout of ALU, its value is “1” when ALU doing arithmetical operations; otherwise, it is “0”. Direction bit determines the direction of shift operation and Type bit determines the way of shifting. Opcode is used to select the type of operation and could be used as input to all three functional units.
Each block shown in the figure should be an independent component that you will route using a port map in your final design (The ALU). Inputs A, B are connected to the three blocks in the ALU: Arithmetic Unit, Shifter Unit and the Logic Unit (not shown).
NOTE:
· The 8-bit multiplier has only 16 bits as output, so the ca
y out of the Arithmetic Unit must be 0 when a multiplication operation is performed.
· The ca
y out of the Arithmetic Unit must be 1 after incremental operation is performed when cu
ent A’s value is 0xFFFF. For example: If cu
ent value of A = 0xFFFF, then A = A + 1 = 0x0000 and ca
y out = 1.
Figure 1: ALU Diagram
The following table summarizes the overall behavior of the ALU:
Mode
Opcode
Operation
0
000
A nor B
0
001
A nand B
0
010
A or B
0
011
A and B
0
100
A xor B
0
101
A xnor B
0
110
Not A
0
111
Not B
1
000
A * B
1
001
A + B
1
010
A – B
1
011
Increment A ( A +1)
1
100
Shift Left(A,B)
1
101
Shift Right(A,B)
1
110
Rotate Left(A,B)
1
111
Rotate Right(A,B)
Your test bench must include a “good” set of test cases that would test the functionality of your designs. Any missing particular case would make you lose points. The test bench is what determines whether your design is working or not. So, make sure you think well about how to
CENG 4354 Digital System Design
CENG 4354 Digital System Design
CENG 4354 Digital System Design
design one.
In your report, make sure to include the VHDL codes of the newly designed components along with their test benches and the commented waveforms. If you are using a previously designed component without any changes, state this in the report and only include source code of the component.
Grading Guidelines:
1. Arithmetic Unit 5 pts
2. Logic Unit 5 pts
3. Shifter Unit 5 pts
4. MUX 5 pts
5. Controller 15 pts
6. Good test bench 10 pts
7. Commented waveforms 10 pts
8. ALU Design 45 pts
Total: XXXXXXXXXX100pts