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Digital Logic Hw-2
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Exercise 3.33 Ben Bitdiddle has designed the circuit in Figure 3.74 to compute a
egistered four-input XOR function. Each two-input XOR gate has a propagation
delay of 100 ps and a contamination delay of 55 ps. Each flip-flop has a setup
time of 60 ps, a hold time of 20 ps, a clock-to-Q maximum delay of 70 ps, and a
clock-to-Q minimum delay of 50 ps.
(a) If there is no clock skew, what is the maximum operating frequency of the circuit?
(b) How much clock skew can the circuit tolerate if it must operate at 2 GHz?
(c) How much clock skew can the circuit tolerate before it might experience a
hold time violation?
(d) Alyssa P. Hacker points out that she can redesign the combinational logic
etween the registers to be faster and tolerate more clock skew. Her improved
circuit also uses three two-input XORs, but they are a
anged differently.
What is her circuit? What is its maximum frequency if there is no clock skew?
How much clock skew can the circuit tolerate before it might experience a
hold time violation?
CLK
lc
CLK
Answered 1 days After Mar 30, 2023

Solution

Baljit answered on Apr 01 2023
29 Votes
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