[61C FA22] 61C Reference Card
Instruction Name Description Type Opcode Funct3 Funct7
add rd rs1 rs2 ADD rd = rs1 + rs2 R XXXXXXXXXX0000
sub rd rs1 rs2 SUBtract rd = rs1 - rs2 R XXXXXXXXXX0000
and rd rs1 rs2 bitwise AND rd = rs1 & rs2 R XXXXXXXXXX0000
or rd rs1 rs2 bitwise OR rd = rs1 | rs2 R XXXXXXXXXX0000
xor rd rs1 rs2 bitwise XOR rd = rs1 ^ rs2 R XXXXXXXXXX0000
sll rd rs1 rs2 Shift Left Logical rd = rs1
rs2 R XXXXXXXXXX0000
srl rd rs1 rs2 Shift Right Logical rd = rs1
rs2 (Zero-extend) R XXXXXXXXXX0000
sra rd rs1 rs2 Shift Right Arithmetic rd = rs1
rs2 (Sign-extend) R XXXXXXXXXX0000
slt rd rs1 rs2 Set Less Than
(signed)
d = (rs1 < rs2) ? 1 : 0 R XXXXXXXXXX0000
sltu rd rs1 rs2 Set Less Than
(Unsigned)
R XXXXXXXXXX0000
addi rd rs1 imm ADD Immediate rd = rs1 + imm I XXXXXXXXXX
andi rd rs1 imm bitwise AND
Immediate
d = rs1 & imm I XXXXXXXXXX
ori rd rs1 imm bitwise OR
Immediate
d = rs1 | imm I XXXXXXXXXX
xori rd rs1 imm bitwise XOR
Immediate
d = rs1 ^ imm I XXXXXXXXXX
slli rd rs1 imm Shift Left Logical
Immediate
d = rs1
imm I* XXXXXXXXXX0000
srli rd rs1 imm Shift Right Logical
Immediate
d = rs1
imm (Zero-extend) I* XXXXXXXXXX0000
srai rd rs1 imm Shift Right Arithmetic
Immediate
d = rs1
imm (Sign-extend) I* XXXXXXXXXX0000
slti rd rs1 imm Set Less Than
Immediate (signed)
d = (rs1 < imm) ? 1 : 0 I XXXXXXXXXX
sltiu rd rs1 imm Set Less Than
Immediate
(Unsigned)
I XXXXXXXXXX
lb rd imm(rs1) Load Byte rd = 1 byte of memory at address
s1 + imm, sign-extended
I XXXXXXXXXX
lbu rd imm(rs1) Load Byte
(Unsigned)
d = 1 byte of memory at address
s1 + imm, zero-extended
I XXXXXXXXXX
lh rd imm(rs1) Load Half-word rd = 2 bytes of memory starting at
address rs1 + imm, sign-extended
I XXXXXXXXXX
lhu rd imm(rs1) Load Half-word
(Unsigned)
d = 2 bytes of memory starting at
address rs1 + imm, zero-extended
I XXXXXXXXXX
lw rd imm(rs1) Load Word rd = 4 bytes of memory starting at
address rs1 + imm
I XXXXXXXXXX
sb rs2 imm(rs1) Store Byte Stores least-significant byte of rs2 at
the address rs1 + imm in memory
S XXXXXXXXXX
sh rs2 imm(rs1) Store Half-word Stores the 2 least-significant bytes of
s2 starting at the address rs1 +
imm in memory
S XXXXXXXXXX
sw rs2 imm(rs1) Store Word Stores rs2 starting at the address
s1 + imm in memory
S XXXXXXXXXX
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CS 61C Reference Card
Version 1.5.0
Instruction Name Description Type Opcode Funct3
eq rs1 rs2 label Branch if EQual if (rs1 == rs2)
PC = PC + offset
B XXXXXXXXXX
ge rs1 rs2 label Branch if Greater or Equal (signed) if (rs1 >= rs2)
PC = PC + offset
B XXXXXXXXXX
geu rs1 rs2 label Branch if Greater or Equal (Unsigned) B XXXXXXXXXX
lt rs1 rs2 label Branch if Less Than (signed) if (rs1 < rs2)
PC = PC + offset
B XXXXXXXXXX
ltu rs1 rs2 label Branch if Less Than (Unsigned) B XXXXXXXXXX
ne rs1 rs2 label Branch if Not Equal if (rs1 != rs2)
PC = PC + offset
B XXXXXXXXXX
jal rd label Jump And Link rd = PC + 4
PC = PC + offset
J XXXXXXXXXX
jalr rd rs1 imm Jump And Link Register rd = PC + 4
PC = rs1 + imm
I XXXXXXXXXX
auipc rd imm Add Upper Immediate to PC rd = PC + (imm
12) U XXXXXXXXXX
lui rd imm Load Upper Immediate rd = imm
12 U XXXXXXXXXX
e
eak Environment BREAK Asks the debugger to do
something (imm = 0)
I XXXXXXXXXX
ecall Environment CALL Asks the OS to do
something (imm = 1)
I XXXXXXXXXX
mul rd rs1 rs2 MULtiply (part of mul ISA extension) rd = rs1 * rs2 (omitted)
Pseudoinstruction Name Description Translation
eqz rs1 label Branch if
EQuals Zero
if (rs1 == 0)
PC = PC + offset
eq rs1 x0 label
nez rs1 label Branch if Not
Equals Zero
if (rs1 != 0)
PC = PC + offset
ne rs1 x0 label
j label Jump PC = PC + offset jal x0 label
jr rs1 Jump Register PC = rs1 jalr x0 rs1 0
la rd label Load absolute
Address
d = &label auipc, addi
li rd imm Load Immediate rd = imm lui (if needed), addi
mv rd rs1 MoVe rd = rs1 addi rd rs1 0
neg rd rs1 NEGate rd = -rs1 sub rd x0 rs1
nop No OPeration do nothing addi x0 x0 0
not rd rs1 bitwise NOT rd = ~rs1 xori rd rs1 -1
et RETurn PC = ra jalr x0 x1 0
XXXXXXXXXX XXXXXXXXXX XXXXXXXXXX XXXXXXXXXX
R funct7 rs2 rs1 funct3 rd opcode
I imm[11:0] rs1 funct3 rd opcode
I* funct7 imm[4:0] rs1 funct3 rd opcode
S imm[11:5] rs2 rs1 funct3 imm[4:0] opcode
B imm[12|10:5] rs2 rs1 funct3 imm[4:1|11] opcode
U imm[31:12] rd opcode
J imm[20|10:1|11|19:12] rd opcode
# Name Description # Name Desc
x0 zero Constant 0 x16 a6 Args
x1 ra Return
Address
x17 a7
x2 sp Stack
Pointe
x18 s2
x3 gp Global
Pointe
x19 s3
x4 tp Thread
Pointe
x20 s4
x5 t0
Temporary
Registers
x21 s5
x6 t1 x22 s6
x7 t2 x23 s7
x8 s0 Saved
Registers
x24 s8
x9 s1 x25 s9
x10 a0 Function
Arguments
or Return
Values
x26 s10
x11 a1 x27 s11
x12 a2
Function
Arguments
x28 t3
x13 a3 x29 t4
x14 a4 x30 t5
x15 a5 x31 t6
S
av
ed
R
eg
is
te
s
Te
m
po
a
ie
s
C
on
tro
l
O
th
e
Caller saved registers
Callee saved registers (except x0, gp, tp)
Immediates are sign-extended to 32 bits, except in I* type instructions and sltiu.
E
xt
SI Prefixes
Size Prefix Symbol Size Prefix Symbol Size Prefix Symbol
10-3 milli- m 103 kilo- k 210 kibi- Ki
10-6 micro- μ 106 mega- M 220 mebi- Mi
10-9 nano- n 109 giga- G 230 gibi- Gi
10-12 pico- p 1012 tera- T 240 tebi- Ti
10-15 femto- f 1015 peta- P 250 pebi- Pi
10-18 atto- a 1018 exa- E 260 exbi- Ei
10-21 zepto- z 1021 zetta- Z 270 zebi- Zi
10-24 yocto- y 1024 yotta- Y 280 yobi- Yi
HEX DEC CHAR HEX DEC CHAR HEX DEC CHAR HEX DEC CHAR HEX DEC CHAR HEX DEC CHAR
0x20 32 SPACE 0x XXXXXXXXXX0x40 64 @ 0x50 80 P 0x60 96 ` 0x70 112 p
0x21 33 ! 0x XXXXXXXXXX0x41 65 A 0x51 81 Q 0x61 97 a 0x71 113 q
0x22 34 " 0x XXXXXXXXXX0x42 66 B 0x52 82 R 0x62 98 b 0x72 114
0x23 35 # 0x XXXXXXXXXX0x43 67 C 0x53 83 S 0x63 99 c 0x73 115 s
0x24 36 $ 0x XXXXXXXXXX0x44 68 D 0x54 84 T 0x64 100 d 0x74 116 t
0x25 37 % 0x XXXXXXXXXX0x45 69 E 0x55 85 U 0x65 101 e 0x75 117 u
0x26 38 & 0x XXXXXXXXXX0x46 70 F 0x56 86 V 0x66 102 f 0x76 118 v
0x27 39 ' 0x XXXXXXXXXX0x47 71 G 0x57 87 W 0x67 103 g 0x77 119 w
0x XXXXXXXXXX0x XXXXXXXXXX0x48 72 H 0x58 88 X 0x68 104 h 0x78 120 x
0x XXXXXXXXXX0x XXXXXXXXXX0x49 73 I 0x59 89 Y 0x69 105 i 0x79 121 y
0x2A 42 * 0x3A 58 : 0x4A 74 J 0x5A 90 Z 0x6A 106 j 0x7A 122 z
0x2B 43 + 0x3B 59 ; 0x4B 75 K 0x5B 91 [ 0x6B 107 k 0x7B 123 {
0x2C 44 , 0x3C 60 < 0x4C 76 L 0x5C 92 \ 0x6C 108 l 0x7C 124 |
0x2D 45 - 0x3D 61 = 0x4D 77 M 0x5D 93 ] 0x6D 109 m 0x7D 125 }
0x2E 46 . 0x3E 62 > 0x4E 78 N 0x5E 94 ^ 0x6E 110 n 0x7E 126 ~
0x2F 47 / 0x3F 63 ? 0x4F 79 O 0x5F 95 _ 0x6F 111 o 0x00 0 NULL
Selected ASCII values
IEEE 754 Floating Point Standard
XXXXXXXXXXSign Exponent Significand
Single Precision 1 bit 8 bits (bias = XXXXXXXXXXbits
Double Precision 1 bit 11 bits (bias = XXXXXXXXXXbits
Quad Precision 1 bit 15 bits (bias = XXXXXXXXXXbits
Standard exponent bias: - (2E-1-1) where E is the number of exponent bits
C Format String Specifiers
Specifier Output
d or i Signed decimal intege
u Unsigned decimal intege
o Unsigned octal
x Unsigned hexadecimal integer,
lowercase
X Unsigned hexadecimal integer,
uppercase
f Decimal floating point,
lowercase
F Decimal floating point,
uppercase
e Scientific notation
(significand/exponent), lowercase
E Scientific notation
(significand/exponent), uppercase
g Use the shortest representation:
%e or %f
G Use the shortest representation:
%E or %F
a Hexadecimal floating point,
lowercase
A Hexadecimal floating point,
uppercase
c Characte
s String of characters
p Pointer address
Laws of Boolean Alge
a
[61C FA22] 61C Reference Card
Instruction Name Description Type Opcode Funct3 Funct7
add rd rs1 rs2 ADD rd = rs1 + rs2 R XXXXXXXXXX0000
sub rd rs1 rs2 SUBtract rd = rs1 - rs2 R XXXXXXXXXX0000
and rd rs1 rs2 bitwise AND rd = rs1 & rs2 R XXXXXXXXXX0000
or rd rs1 rs2 bitwise OR rd = rs1 | rs2 R XXXXXXXXXX0000
xor rd rs1 rs2 bitwise XOR rd = rs1 ^ rs2 R XXXXXXXXXX0000
sll rd rs1 rs2 Shift Left Logical rd = rs1
rs2 R XXXXXXXXXX0000
srl rd rs1 rs2 Shift Right Logical rd = rs1
rs2 (Zero-extend) R XXXXXXXXXX0000
sra rd rs1 rs2 Shift Right Arithmetic rd = rs1
rs2 (Sign-extend) R XXXXXXXXXX0000
slt