Great Deal! Get Instant $10 FREE in Account on First Order + 10% Cashback on Every Order Order Now

Project_2 Second Programming Assignment Suppose we have a vending machine that sells Pringles cans that costs 2$ each. Moreover, the machine only accepts three types of coins: 1$, 2$ and 5$. Note: You...

1 answer below »
Project_2
Second Programming Assignment
Suppose we have a vending machine that sells Pringles cans that costs 2$
each. Moreover, the machine only accepts three types of coins: 1$, 2$ and
5$.
Note: You can assume there are infinite number of cans in the machine
stock.
You can also assume that you can input one type of coins at every
deposit. (You cannot deposit 1$ AND 5$ at the same time.)
Cases:
1) You input NO coin.
2) Putting 1$ followed by another 1$ => getting the can
3) Putting 1$ followed by 2$ => receive the change => getting the can
4) Putting 1$ followed by 5$ => receive the change => getting the can
5) Putting 2$ => getting the can
6) Putting 5$ => receive the change => getting the can.
Please implement this finite state machine (FSM) using VHDL. First, please
provide the state transition diagram of Mealy/Moore Machine you are
implementing. Explain the details. Finally, provide a wave-form for EACH
cases given to you in the description.
You may pair up with another student in your OWN section. Please submit
ONE pdf file that contains all the details.
Deadline: Sunday, May 31st 11:59pm. NO EXTENSION WILL BE
GRANTED.
Please take a two-minute video of you sharing and explaining your
code. Please use a screen share program with this purpose and I’m
sure you can find many free softwares to record your screen.
Please run your code and also show me the created wave-forms. If
you have problems with installing ModelSim software, please pair up
with someone who has no problem with that.
If you do NOT upload your video by the deadline, NO POINT will be
given to you.
Answered Same Day May 26, 2021

Solution

Sandeep Kumar answered on May 29 2021
142 Votes
We will design a mealy machine which has two states. RESET and OD (represents reception of 1$). The following assumptions are made to proceed with the state machine design
· Inputs are represented in 2 bit binary format with following assumptions
· Outputs are represented in 3 bit binary format with the least significant bit represents getting can (if it is 0, getting no can and if it is 1 represents getting 1 can) and upper two bits represents getting change (00 represents getting no change, 01 represent...
SOLUTION.PDF

Answer To This Question Is Available To Download

Related Questions & Answers

More Questions »

Submit New Assignment

Copy and Paste Your Assignment Here