Assembly Program You will have 45 minutes to complete this part of the exam. You may use your textbook for this part of the Final Exam. Instructions: This is similar to the IRQ interrupt example...

Assembly Program
You will have 45 minutes to complete this part of the exam. You may use your textbook for this part of the Final Exam.
Instructions:
This is similar to the IRQ inte
upt example program in the Unit 5 Lecture 8. Please use CodeWa
ior to write an assembly program to do the followings:
· Turn on only LED0 and LED7 continuously during the normal operation.
· Turn on all LEDs whenever there is XIRQ inte
upt.
· Go back to normal operation after no more inte
upt.
· This process continues until a Reset.
Suggestions:
· You should type in the example program on IRQ inte
upt that is in the Unit 5 Lecture 8, assemble it, download it, and test it. Understand this example program completely by reading the Unit 5 Lecture 8, on IRQ and by testing the example program.
· Then, read Unit 5 Lecture 8 slides on XIRQ inte
upt, and modify the main: delete the code for enabling low-level triggering and for enabling IRQ pin, and add code to enable XIRQ pin, and clear the X bit (bit 6) in CCR.
· Change the service routine name from IRQ_ISR to XIRQ_ISR; Set up inte
upt vector for XIRQ_ISR (Please understand how IRQ_ISR is set up in the example program, and do it similarly to set up XIRQ_ISR using the XIRQ inte
upt vector),
After you have successfully assembled your program, and debugged your program, download your program, and test your program.
Notes:
PAGE

Eet430 Microcontrollers
EET430 Microcontrollers
Lecture 8
HCS12’s Inte
upts, and
Its Assembly Programming
Dr. Ning Hu
ECPI University
Outline
 HCS12’s Inte
upt concept
 HCS12’s Inte
upt Vector Table
 Mask(Disable)/Enable Inte
upts Globally
 Enable/Disable an Inte
upt locally
 External Hardware/Internal Hardware Inte
upts
 HCS12 Inte
upt Priority
 HCS12 Inte
upt Programming
 Programming HCS12 Timer Systems by Inte
upts
 Lab 8
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The Goal of the Course
1. To understand Microcontroller in general,
and HCS12 in particula
2. To be able to program the HCS12
Microcontrollers to control external
devices
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How to Achieve the Goal?
 Must learn the following:
1. Hardware of the Microcontrollers: Memory
maps, CPU registers, and I/O ports
2. Software of the Microcontrollers: Addressing
modes, and Instruction Set
3. Programming skills: Sequences, loops, and
anches (IF – ELSE)
4. Tools: CodeWa
io
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What is An Inte
upt?
 An event that causes the CPU to suspend
whatever it is doing, and to handle this event.
Such an event is called an inte
upt.
 Inte
upts can occur at any time, because the
events that cause inte
upts can happen at any
time.
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Inte
upt Service Routines (ISR)
 The way that a CPU handles an inte
upt is by
executing a special program that is written jus for this
inte
upt. Such a special program is called Inte
upt
Service Routine (ISR) or Inte
upt handler.
 An inte
upt service routine (ISR) is not a simple
su
outine.
 An inte
upt service routine (ISR) differs from a
su
outine in that it is pre-coded and stored in
specified locations of the Memory.
 The last instruction in an ISR is RTI (not RTS).
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Inte
upt Vectors
 For every inte
upt, a fixed two-byte memory location is
eserved for it. This reserved two-byte memory location
is called its inte
upt vector;
 For example, the inte
upt vector for Reset is the last
two bytes $FFFE, $FFFF, or vector ($FFFE, $FFFF).
 The two bytes in an inte
upt vector are used to hold the
starting address of the associated inte
upt service
outines.
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Inte
upt Vector Table
 HCS12 microcontrollers set aside a block of memory to
host all the inte
upt vectors. This block of memory is
called the inte
upt vector table;
 An inte
upt vector table is typically in a EEPROM.
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HCS12 Inte
upt Vector Table
9
Partial Listing of Inte
upt Vector Table for the HCS12
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Inte
upts and CCR
10
The I bit and X bit in the CCR Registe
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Resets and Inte
upts
 HCS12’s inte
upts can be
oadly classified
into two categories:
1) Resets;
2) Inte
upts;
 Resets can be regarded as special
inte
upts;
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HCS12’s Resets
 There are four resets:
1) Power-on reset;
2) Computer Operating Properly (COP) reset;
3) Clock Monitor reset;
4) External reset (the reset button);
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HCS12’s Inte
upts
The regular inte
upts of HCS12 can be futher divided into following
two categories:
 Software inte
upt – HCS12 provides only one software inte
upt,
called SWI, which is an instruction. Whenever this instruction is
executed, the co
esponding ISR at location $$FFF6 and FFF7 is
executed;
 Hardware inte
upts – Except SWI, all the other regular inte
upts
are classified as hardware inte
upts (more details on next slide);
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HCS12’s Hardware Inte
upts
 External hardware inte
upts - two pins associated
with such hardware inte
upts: IRQ and XIRQ.
 Invalid instruction exception (trap) - an exception
inte
upt, invoked internally when there are conditions
a CPU is unable to handle, such as invalid opcode.
 Peripheral inte
upts – occurs as the result of a
condition set by a peripheral module such as HCS12’s
timer system or HCS12’s analog-to-digital converter
module.
 The majority of HCS12’s inte
upts belongs to
Peripheral inte
upts category.
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Maskable Inte
upts
 An Inte
upt is called maskable inte
upt if it can be masked out
(disabled) by setting a specific bit.
 Such an maskable inte
upt can also be unmasked (enabled) by
clear this bit;
 Most of the HCS12’s inte
upts are maskable.
Someone suddenly open your door is an inte
upt. You can mask out
such an inte
upt by locking the door from inside. Or, you can enable
such inte
upt by unlocking the door from inside.
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Mask/Enable Inte
upts Globally
 Most of the HCS12’s inte
upts are maskable
as a group – meaning they can be disabled as
a group:
 This group is called maskable group;
 To mask the entire group, set (SEI) the I bit in CCR;
 To enable/un-mask the entire group, clear (CLI) the I
it in CCR.
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Enable/disable an individual Inte
upt
 Most of HCS12;s inte
upts can also be
enabled/disabled individually by setting or clearing its
local enable bit;
 If I bit in CCR is cleared, then, set the local enable bit for
an inte
upt will enable the inte
upt, and clear this bit
will disable this inte
upt;
 If I bit in CCR is set, then, the entire maskable group is
disabled regardless the status of the local bits for each
individual inte
upt.
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Steps In Handling An Inte
upt
 HCS12 will follow following steps when handling an inte
upt: Upon
eceiving an inte
upt signal, the CPU will
1. suspend the execution of the cu
ent program;
2. push all the CPU registers onto Stack;
3. Jump to and execute the associated inte
upt service
outine(ISR);
4. after CPU executing the last instruction in ISR, which is RTI, it
will restore the CPU registers;
5. resume the execution of the suspended program.
 These steps only apply to regular inte
upts, not apply
to resets.
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HCS12 CPU Register Stacking Orde
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External Hardware Inte
upt: IRQ
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External Hardware Inte
upt:
IRQ
 IRQ inte
upt vector: ($FFF2, $FFF3) ;
 Pin PE1of PORTE is used to send an IRQ input signal;
 IRQ is part of the group of the maskable inte
upts that
can be enabled/disabled globally by the I bit of the
CCR.
 To enable IRQ globally, use instruction CLI
 To mask out (disable) IRQ, use instruction SEI
 To use IRQ, it must also be enabled locally;
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External Hardware Inte
upt: IRQ (cont.)
 IRQ can be triggered by either an active-low level or by a
high-to-low falling-edge;
 We must configure INTCR register to enable IRQ locally,
and to choose triggering mode.
22
Inte
upt Control Register: INTCR
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External Hardware Inte
upt: IRQ (cont.)
 Level-triggered IRQ - In the level-triggered mode, the
IRQ pin is normally high, and if a low-level signal is
applied to it, it triggers the inte
upt.
 The IRQ pin must be
ought back to high by the time
RTI is executed.
 Using level-triggered inte
upt allows us to tie together
inte
upts from several sources & feed it to the IRQ pin.
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External Hardware Inte
upt: IRQ (cont.)
 Edge-triggered IRQ - IRQE bit in the INTCR
determines if IRQ is triggered by an active-low level or
a falling-edge.
 Instruction: BSET INTCR, % XXXXXXXXXXmakes IRQ an
falling-edge triggered inte
upt.
 assuming that the I bit in the CCR register is cleared;
 a high-to-low signal applied to pin PE1 will inte
upt the
controller and force it to use its inte
upt vector ($FFF2, $FFF3)
to jump to its ISR;
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An Example of IRQ Inte
upt Programming
Please write an assembly program to do the
followings:
 Turn on only LED0 and LED7 continuously during the
normal operation;
 Turn on all LEDs whenever there is a active-low IRQ
inte
upt;
 Go back to normal operation after no more inte
upt;
 This process continues until a Reset.
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The Screen Shot of the Example Program:
The Main Program
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The Screen Shot of the Example Program:
The IRQ Inte
upt Service Routine
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External Hardware Inte
upt: XIRQ
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External Hardware Inte
upt: XIRQ
 XIRQ inte
upt vector: ($FFF4, $FFF5);
 Pin PE0 of PORTE is used to send an input
signal for XIRQ inte
upt;
 After enabling the XIRQ (X bit = 0 in CCR), it
cannot be disabled;
 Thus, it is also called non-maskable inte
upt;
 The only way to disabled it again is to reset the
controller;
 XIRQ is triggered only by an active-low level.
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External Hardware Inte
upt: XIRQ (cont.)
 To enable and use XIRQ, X-bit in CCR must be cleared.
 To clear X-bit: ANDCC #$BF
Note 1: $BF = % XXXXXXXXXXThe above code logically AND CCR with
$BF, which clears X (bit 6 in CCR).
Note2: XIRQ is non-maskable. So, unlike IRQ, CLI and SEI have no
effect on XIRQ.
Note3: Unlike IRQ, no need to configure any registers when using
XIRQ.
 Can you write a program for XIRQ similar to the example program
for IRQ?
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Other External Hardware Inte
upts
 In addition to IRQ and XIRQ external hardware
inte
upts, HCS12 microcontrollers also allow us to use
PTH (port