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Please explain how to do so step by step Need a lot of help! Thank you! Consider an 8-bit shifting circuit that can perform rotating right or rotating left. An additional 1-bit control signal, lr,...

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Please explain how to do so step by step Need a lot of help! Thank you!

Consider an 8-bit shifting circuit that can perform rotating right or rotating left. An additional 1-bit control signal, lr, specifies the desired direction. Design the circuit using one rotate-right circuit, one rotate-left circuit, and one 2-to-1 multiplexer to select the desired result. Derive the code. Derive a testbench and use simulation to verify operation of the code. Synthesize the circuit, program the FPGA, and verify its operation. This circuit can also be implemented by one rotate-right shifter with pre- and post-reversing circuits. The reversing circuit either passes the original input or reverses the input bitwise (e.g., if an 8-bit input is a_7a_6a_5a_4a_3a_2a_1a_0, the reversed result becomes a_0a_1a_2a_3a_5a_5a_6a_7). Repeat steps 2 and 3. Check the report files and compare the number of logic cells and propagation delays of the two designs.
Answered 134 days After May 14, 2022

Solution

Banasree answered on Sep 26 2022
67 Votes
ans.
TO ROTATE LEFT
li
ary ieee;
use ieee.std_logic_1164.all;
entity rotate_l is
port(clk:in std_logic;
data_in: in std_logic_vecto(7downto 0);
data_out:out std_logic_vector(7downto 0));
end rotate_l;
architecture arch of rotate_l is
egin
process(clk)
egin
if(clk’event and clk=’1’)then
data_out<=data_in(6downto 0)&data_in(7);
end if;
end process;
end arch;
otate right
li
ary ieee;
use ieee.std_logic_1164.all;
entity rotate_r is
port(clk:in std_logic;
data_in: in std_logic_vecto(7downto 0);
data_out:out std_logic_vector(7downto 0));
end rotate_r;
architecture arch of rotate_r is
egin
process(clk)
egin
if(clk’event and clk=’1’)then
data_out<=data_in(0) & data_in(7 downto 1)
end if;
end process;
end arch;
MULTIPLEXER
li
ary ieee;
use ieee.std_logic_1164.all;
entity multiplexer2to1is
port(lr:in std_logic;
data_l: in std_logic_vector(7downto...
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