https:
eclass.yorku.ca/pluginfile.php/4000486/mod_resource/content/2/LabK_EECS2021_VerilogLab4_F2022_v1_student_VERSION
EECS 2021 – Lab K: Build another CPU 2022 Student VERSION
EECS 2021 – Lab K: CPUs, Take 2
(Verilog Lab #4)
Dr. James Andrew Smith, PEng.
(a modification of original lab by Dr. Hamzeh Roumani)
Summary: You modelled an 8-bit or 32-bit CPU in the previous lab. Now, get more
practice, extending your knowledge to 4-bits or 16-bits.
Pre-Lab: You will have done all or most of Lab J. If you did not complete Lab J, move
on and complete this lab, but rather than an 8- or 32-bit machine, you’re now looking at 4-
it or 32-bit.
Intro to Verilog video on YouTube
(https:
youtu.be/3ZJNV9F3AB4)
Simulink as a Circuit Simulator (https:
youtu.be/NSbPNoVWMfU)
An example logic circuit (in schematic form). An example logic circuit (in Verilog form)
Due date for Lab Report. No report
Lab Demo and Demo Grading: The lab is worth one mark.
Demo 1: [0.5 marks]
Full & co
ect demo of the module? 0.3 marks. Partially successful demo? 0.2 marks. 0 otherwise
• Last name V-Z: demo Part 2 from Lab J (combine mux’s into a bus), but either 4-bit or 16-bit.
• Last name A-G: demo Part 3 from Lab J (a
ay based mux), but either 4-bit or 16-bit.
• Last name H-M: demo Part 4 from lab J (4to1 mux), but either 4-bit or 16-bit.
• Last name: N-U demo Part 5 from Lab J (full adder), but either 4-bit or 16-bit.
Demo 2: [0.5 marks]
• Demo the entire CPU (either 4-bits or 16-bits), as you did in Lab J.
o Partial demo? 0.2 marks
o No demo? 0.
No demo? No mark in that category. Partial demo (doesn’t compile, at least one e
or in test): 50% for that category.
EECS 2021 – Lab K: Build another CPU 2022 Student VERSION
General Remote Lab Instructions
While EECS 2021 students would normally use the
Verilog tools in PRISM Centre of the Lassonde
Building, Room 1004 and Room 1006, you can also
access them via the EECS Remote Lab web
interface system, a traditional SSH connection from
Windows PowerShell or macOS Terminal, or on the
web via EDA Playground.
When editing your Verilog files (*.v) you can either
edit
a. Within EDA Playground
. On an editor in the SSH session (like vim, nano or emacs), either within
emotelab.eecs.yorku.ca, or within an ssh session from Windows PowerShell,
macOS Terminal, etc.
c. Using an editor on your own personal computer that supports SFTP or
equivalent (e.g. BBEdit, Textwrangler, EditPlus, etc.)
Also, consider using Matla
Simulink to simulate the any unfamiliar components or
circuits before implementing the Verilog solution. The reason? A graphical tool like
Simulink will help you lay out your parts and help you see how the system is supposed to
work before writing up the text-based script. If something goes wrong you can look at
Simulink to help debug and understand.
Figure 1 Using graphical tools like Simulink or MapleSim to quickly examine your circuit ahead of time is helpful.
EECS 2021 – Lab K: Build another CPU 2022 Student VERSION
The Lab
This is continuation of the first Verilog lab. You can model the circuits in this lab using a
number of different Verilog solutions, including
1. The internal (to YorkU) SSH or GUI interface for remotelab.eecs.yorku.ca
2. The external (to YorkU) commercial system, EDA Playground
(edaplayground.com)
The methods for implementation are slightly different due to the nature of the interfaces,
ut they can produce the same results.
Part 1: Get to the mid-point in either a 4-bit or 16-bit system
You are asked to do two demonstrations in this lab. Both are similar to Lab J. First, you
are to demonstrate a component in the construction of either a 4-bit or 16-bit computer.
Either
• demo Part 2 from Lab J (combine mux’s into a bus), either 4-bit or 16-bit.
• demo Part 3 from Lab J (a
ay based mux), either 4-bit or 16-bit.
• demo Part 4 from lab J (4to1 mux), either 4-bit or 16-bit.
• demo Part 5 from Lab J (full adder), either 4-bit or 16-bit.
Where the selection and marks associated with the demo are on the first page of this
document.
Example 4-bit project in EDA Playground Example 16-bit project in EDA Playground
EECS 2021 – Lab K: Build another CPU 2022 Student VERSION
Part 2: The CPU (4-bit or 16-bit)
Having followed all the steps from Lab J, now combine the components to form
either a 4-bit or 16-bit CPU. This is similar to the last step in Lab J, in which you
were to have finished up with an 8-bit or 32-bit machine.
Demo to the TA that you can successfully test the CPU (either 4-bit or 16-bit)
using opcodes 6 or 7.
https:
eclass.yorku.ca/pluginfile.php/4000468/mod_resource/content/2/LabJ_EECS2021_VerilogLab2_F2022_v1_Student_VERSION
EECS 2021 – Lab J: Build a CPU 2022 Student VERSION
EECS 2021 – Lab J: CPUs: From Busses to ALUs
(Verilog Lab #3)
Dr. James Andrew Smith, PEng.
(a modification of original lab by Dr. Hamzeh Roumani)
Summary: Let’s model circuits (like a mux) that have groups of multiple signal
wires (e.g. a bus). This is the next stage in developing CPU-relevant components using
Verilog.
Pre-Lab: You are to prepare for the lab by reading over this document and by conducting
Lab I. You may wish to peruse online sources of Verilog tutorials, as well.
Intro to Verilog video on YouTube
(https:
youtu.be/3ZJNV9F3AB4)
Simulink as a Circuit Simulator (https:
youtu.be/NSbPNoVWMfU)
An example logic circuit (in schematic form). An example logic circuit (in Verilog form)
EECS 2021 – Lab J: Build a CPU 2022 Student VERSION
Marking Guide
Lab Report [ 1 mark ]
Single page report (PDF) submitted to eClass. Name of the course
and your name and student ID at the top.
Draw
• the “4 to 1” Mux and [0.5 marks]
• “full adder” schematics [0.5 marks]
as described in this lab, by hand (either on paper or using a
drawing program like OneNote, but not a CAD program like
Proteus) labelling all the wires, including inputs, outputs and wires in between
components in a way that makes it clear that it could be implemented in Verilog. It is
due on the Sunday after your lab.
If the drawing has any e
ors in it, is difficult to read, or is mislabelled, then it is 0.25
marks for that drawing. 0 if no drawing submitted.
Lab Demo [ 1 mark ]
The lab is worth one mark with two demonstrations.
Demo 1: [0.8 marks]
• Last name A-G: demo Part 2 (combine mux’s into a bus), either 8-bit or 32-bit. (0.7 marks)
• Last name H-M: demo Part 3 (a
ay based mux), either 8-bit or 32-bit. (0.7 marks)
• Last name N-U: demo Part 4 (4to1 mux), either 8-bit or 32-bit. (0.7 marks)
• Last name V-Z: demo Part 5 (full adder), either 8-bit or 32-bit. (0.7 marks)
Full demo of the component needed for 0.7 marks.
Partial demo (doesn’t compile, at least one e
or in test, etc.): 0.35 marks.
The TA will ask you to explain the component that you are demonstrating. The TA will
evaluate you on the proficiency of the answer:
• Failing to meet expectations: No answer or no understanding of the component 0 / 0.1
• Marginally meet expectations: Student shows some understanding 0.05 / 0.1
• Meet expectations: Student understands the component 0.1 / 0.1
Demo 2: [0.2 marks]
For the final 0.2 marks, demonstrate the entire CPU, either 8-bit or 32-bit.
EECS 2021 – Lab J: Build a CPU 2022 Student VERSION
General Remote Lab Instructions
While EECS 2021 students would normally use the
Verilog tools in PRISM Centre of the Lassonde
Building, Room 1004 and Room 1006, you can also
access them via the EECS Remote Lab web
interface system, a traditional SSH connection from
Windows PowerShell or macOS Terminal, or on the
web via EDA Playground.
When editing your Verilog files (*.v) you can either
edit
a. Within EDA Playground
. On an editor in the SSH session (like vim, nano or emacs), either within
emotelab.eecs.yorku.ca, or within an ssh session from Windows PowerShell,
macOS Terminal, etc.
c. Using an editor on your own personal computer that supports SFTP or
equivalent (e.g. BBEdit, Textwrangler, EditPlus, etc.)
Also, consider using Matla
Simulink to simulate the any unfamiliar components or
circuits before implementing the Verilog solution. The reason? A graphical tool like
Simulink will help you lay out your parts and help you see how the system is supposed to
work before writing up the text-based script. If something goes wrong you can look at
Simulink to help debug and understand.
Figure 1 Using graphical tools like Simulink or MapleSim to quickly examine your circuit ahead of time is helpful.
EECS 2021 – Lab J: Build a CPU 2022 Student VERSION
The Lab
This is continuation of the first Verilog lab. You can model the circuits in this lab using a
number of different Verilog solutions, including
1. The internal (to YorkU) SSH or GUI interface for remotelab.eecs.yorku.ca
2. The external (to YorkU) commercial system, EDA Playground
(edaplayground.com)
The methods for implementation are slightly different due to the nature of the interfaces,
ut they can produce the same results.
Part 1: Looking at the MUX again.
1. In a previous lab we created the 2-to-1 mux
shown in the left part of the figure below and
found that it acts as an if statement.
In this lab we will use abstraction to
encapsulate this circuit as a reusable component so that it can
e used by someone who doesn't know how it works internally.
Let us adopt the diagram shown in the right part of the figure
as an abstraction of what this circuit does: a box with two
doors, labelled 0 and 1, and a control input c. The control is so
named because it actually controls the circuit: if it is =0 then
Door-0 would open and z would be a. Otherwise z would be b.
We will call the component yMux1.
2. Either with the (a) command line version of iVerilog on
RemoteLab or (b) with EDA Playground set to iVerilog,
create the Verilog model file “program” yMux1.v as follows:
Import the Multiplexor (MUX) circuit
The yMux1.v file defines the module.
It will be linked in.
yMux1 is a “type” defined in that file.
my_mux() is an instance of the type yMux1
z is an output; a, b, and c are inputs to the mux.
yMux1 my_mux(z, a, b, c);
“Importing” an instance of a module. In your Verilog
“test bench” file you can create an instance of the
mux that has been defined in a separate file,
yMux1.v. This is how you allow that mux to be
tested within the test bench. See the EDA
Playground screenshot below for placement within
the test bench Verilog file.
Compare this with the testing modules we wrote earlier. Note that the circuit's ports
are listed in the module statement and that a special declaration is used to indicate
their “in” or “out” status. Note also the absence of any initial block. In a way, this
Figure 2 If you're using EDA
Playground, press the "+" symbol to
create a new file.
EECS 2021 – Lab J: Build a CPU 2022 Student VERSION
module to a testing module is like a li
ary class to an app with a main method.
3. Using Part 8 of Lab I as your starting point, create the
program LabJ.v that instantiates and tests yMux1.
Treat this component the same as a built-in one. Include
a testing regime. How to test? You can do
a) manual testing,
b) via command-line arguments, or
c) an exhaustive, three-nested-loop test (shown below
in EDA Playground)
Skip ahead if you’re using EDA Playground. If you’re
unning from the command line, compile your program
using the command:
iverilog LabJ_part1.v
This command searches for a module that defines yMux1 and compiles it, together
with LabJ_part1.v, to produce a single executable file named a.out. Alternatively,
you can specify the names of the needed modules explicitly on the command line:
iverilog LabJ_part1.v yMux1.v
4.
Run the model. If you’re using the command line, use vvp to run your Verilog
model “program” and ensure that the multiplexor (“mux”) module behaves as
expected. You can also use EDA Playground to run the simulation:
Figure 4 Rather than use the command line you can use EDA Playground to examine the mux, even if you have the
mux defined in a separate file, as shown here. We use a three level loop to run the “exhaustive testing”.
Figure 3 You can do command-line arguments
in EDA Playground, too. For instance, in this
example, put the arguments in the Run box like
this: a.out +a=1 +b=0 +c=0
EECS 2021 – Lab J: Build a CPU 2022 Student VERSION
Part 2: Combine two Mux’s to control a “Bus”
What if, with a single command signal, c, you could
control the flow of two different output signals, z0 and z1?
You can! Given that one mux can control the flow of one
signal, if you have two mux’s, both connected to the
same control signal, c, you can control the flow of signals
into z0 and z1 at the same time. For instance, if c is 0,
then the first output wire z0 will output a0 and second
output wire z1 will output a1.
5. We call a bundle of related wires a “bus”. As shown in
Figure 5 we seek to enhance our mux so it can handle
2-bit busses instead of 1-bit wires, as