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1 Computer Architecture Design of Combination Logic Circuits with VHDL and Quartus Prime A. MATERIAL • Intel Quartus Prime & ModelSim Altera. B. OBJECTIVE Using Intel...

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1

Computer Architecture
Design of Combination Logic Circuits with VHDL and Quartus Prime
A. MATERIAL

• Intel Quartus Prime & ModelSim Altera.

B. OBJECTIVE

Using Intel Quartus, implement the combination logic circuits in VHDL. When asked,
provided the manual solution.
C. COMBINATIONAL LOGIC

1) Considering the following truth table, do the following:
a) Using SOP, find the output Y and its optimized version with the least number of logic gates.
Sketch your design. Show your work.
) Code the VHDL design using concu
ent signal assignment, i.e., express the output Y as a
function of the minterms. Copy and paste the code as well as the schematic originated from the
computer aid tool (CAD).
c) Code the VHDL design using Conditional Signal Assignment with when/else statements.
Copy and paste the code as well as the schematic originated from the computer aid tool (CAD).
d) Code the VHDL design using Selected Signal Assignment (with … select). Copy and paste the
code as well as the schematic originated from the computer aid tool (CAD).
e) Simulate the output considering one of the implemented designs and verify for co
ectness
of the circuit. This can be done differently, for instance, by comparing the output of the
simulation with the truth table. Explain your analysis.
2
2) Considering the following truth table, do the following:
a) Using SOP, find the output Y and its optimized version with the least number of logic gates.
Sketch your design. Show your work.
) Code the VHDL design using concu
ent signal assignment, i.e., express the output Y as a
function of the minterms. Copy and paste the code as well as the schematic originated from the
computer aid tool (CAD).
c) Code the VHDL design using Conditional Signal Assignment with when/else statements.
Copy and paste the code as well as the schematic originated from the computer aid tool (CAD).
d) Code the VHDL design using Selected Signal Assignment (with … select). Copy and paste the
code as well as the schematic originated from the computer aid tool (CAD).
e) Simulate the output considering one of the implemented designs and verify for co
ectness
of the circuit. This can be done differently, for instance, by comparing the output of the
simulation with the truth table. Explain your analysis.
3
    a. Material
    b. Objective
    C. COmbinational Logic

comparch-l4jhgx45.pdf

Answered 3 days After Feb 28, 2023

Solution

Sathishkumar answered on Mar 01 2023

32 Votes

1.
a.
(A’B’C’D’) + (A’B’CD’) + (A’B’CD) + (A’BCD’) + (A’BCD) + (AB’C’D’) + (AB’CD’)
Minimization Steps
= A’ * B’ * (C’ * D’ + C * D’ + C * D) + A * B’ * (C’ * D’ + C * D’)
= A’ * B’ * (D’ + C) + A * B’ * C
= A’ * B’ * D’ + A’ * B’ * C + A * B’ * C
= A’ * B’ * D’ + A’ * B’ * C
y = B'D' + A'C
.
li
ary ieee;
use ieee.std_logic_1164.all;
entity Boolean_expression is
port (
A, B, C, D : in std_logic;
F : out std_logic
);
end entity Boolean_expression;
architecture Behavioral of Boolean_expression is
egin
F <= (not A and not B and not C and not D) o
(not A and not B and C and not D) o
(not A and not B and C and D) o
(not A and B and C and not D) o
(not A and B and C and D) o
(A and not B and not C and not D) o
(A and not B and C and not D);
end architecture Behavioral;
c.
li
ary ieee;
use ieee.std_logic_1164.all;
entity y_expression1 is
port (
A, B, C, D : in std_logic;
F : out std_logic
);
end entity y_expression1;
architecture Behavioral of y_expression1 is
egin
F <= '1' when (not A and not B and not C and not D) = '1' else
'1' when (not A and not B and C and not D) = '1' else
'1' when (not A and not B and C and D) = '1' else
'1' when (not A and B and C and not D) = '1'...

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